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Watchdog Timer
14-4
14.3 Watchdog Timer
The watchdog timer is used to ensure that the CPU is executing the user
program and not some random sequence of instructions provoked by a
malfunction. When the watchdog timer is enabled, the user program must
periodically notify the watchdog that the program is still running correctly. If the
watchdog detects that the user program has not made this notification after a
certain amount of time, the watchdog automatically resets the MCS1210 or
executes an interrupt. This ensures that the part does not hang in an infinite loop
or execute non-program code due to some malfunction or programming error.
Figure 14−2. System Timing Interrupt Control
14.3.1 Watchdog Timer Hardware Configuration
The watchdog is first configured when code is downloaded to the MSC1210.
Bit 3 of hardware configuration register 0 (HCR0) is the Enable Watchdog
Reset (EWDR) bit. If this bit is set, the watchdog will trigger a reset (if the
watchdog is enabled by software and not reset at appropriate intervals),
whereas if this bit is clear, the watchdog will trigger an interrupt (if the watchdog
is enabled by software not reset at appropriate intervals). The point to
remember is that the EWDR bit in the HCR0 register indicates what the
watchdog will do when it is triggered: reset the MSC1210 or cause an interrupt.
It does not, by itself, enable or disable the watchdog; that is done in software
at execution time.
- User’s Guide 1
- 3
- Contents 10
- Contents 11
- Contents 11
- Chapter 1 13
- 1.1 MSC1210 Description 14
- 1.2 MSC1210 Pin-Out 15
- MSC1210 Pin-Out 19
- Introduction to the MSC1210 19
- 1.2.3 Reset Line (RST) 22
- 1.2.6 External Access (EA) 23
- 1.3 Enhanced 8051 Core 24
- 1.5 Flash Memory 25
- High-Performance Peripherals 26
- 27
- 2.1 Description 28
- 2.2 Program Memory 28
- 2.3 Data Memory 30
- 2.3.3 External Data Memory 31
- 2.4 Internal RAM 32
- 2.4.1 The Stack 33
- 2.4.2 Register Banks 33
- 2.4.3 Bit Memory 34
- MOV P0,#01h 35
- SETB 80h 35
- MOV 50h,#01h 36
- MOV 99h,#01h 36
- Chapter 3 37
- 3.1 Description 38
- 3.2 Referencing SFRs 39
- 3.3 Bit−Addressable SFRs 40
- 3.4 SFR Types 40
- 3.5 SFR Definitions 41
- , Address E6 48
- " 51
- 4.1 Description 52
- 4.2 Accumulator 52
- 4.3 R Registers 52
- 4.4 B Register 53
- 4.5 Program Counter (PC) 53
- 4.7 Stack Pointer (SP) 54
- # 55
- 5.1 Description 56
- 5.2 Immediate Addressing 56
- 5.3 Direct Addressing 57
- 5.4 Indirect Addressing 58
- External Direct Addressing 59
- Addressing Modes 59
- 5.7 Code Indirect Adressing 60
- $ % 61
- 6.1 Description 62
- 6.2 Conditional Branching 62
- 6.3 Direct Jumps 62
- LJMP NEW_ADDRESS 63
- NEW_ADDRESS: 63
- 6.4 Direct Calls 64
- 6.5 Returns From Routines 64
- 6.6 Interrupts 64
- 65
- 7.1 Description 66
- System Timing 67
- 7.2 System Timers 68
- System Timers 69
- 7.2.1 Microseconds Timer 70
- 7.2.2 Milliseconds Timer 70
- 7.3 Startup Timing 73
- Chapter 8 75
- 8.1 Description 76
- 8.2 How Does a Timer Count? 76
- 8.3.2 Timer SFRs 78
- Table 8−1.Timer Conrol SFRs 78
- 8.3.3 TMOD SFR 79
- 8.3.4 TCON SFR 82
- Table 8−4.TCON (88 82
- 8.3.5 Initializing a Timer 83
- 8.3.6 Reading the Timer 83
- MOV A,TH0 84
- MOV R0,TL0 84
- CJNE A,TH0,REPEAT 84
- Using Timers to Measure Time 85
- ;keep waiting 86
- ;right now 86
- 8.5 Using Timer 2 87
- Using Timer 2 88
- 8.5.3 Timer 2 in Capture Mode 89
- 91
- 9.1 Description 92
- Setting the Serial Port Mode 100
- Serial Communication 101
- MOV SBUF0,#’A’ 105
- 9.5 Reading the Serial Port 106
- 107
- 10.1 Description 108
- Table 10−1.Interrupt Sources 109
- 10.3 Enabling Interrupts 111
- 10.4 Polling Sequence 112
- 10.5 Interrupt Priorities 113
- 10.6 Interrupt Triggering 114
- 10.7 Exiting Interrupts 114
- 10.8 Types of Interrupts 115
- Table 10−7.EXIF (91 116
- 10.8.3 Timer Interrupts 117
- 10.8.4 Watchdog Interrupt 117
- 10.8.5 Auxiliary Interrupts 117
- Table 10−9.AIE (A6 118
- Table 10−10. AISTAT (A7 119
- Table 10−11. PAI (A5 119
- 10.9 Waking Up from Idle Mode 121
- 10.10 Register Protection 122
- Chapter 11 125
- 11.1 Description 126
- 11.2 Tone Generator 127
- 11.3 PWM Generator 129
- PWM Generator 130
- Statement # Explanation 132
- Figure 11−6. PWM Timing 135
- #))* + 137
- 12.1 Description 138
- 12.2 Input Multiplexer 139
- 12.3 Temperature Sensor 141
- 12.4 Burnout Current Sources 143
- 12.5 Input Buffer 144
- With the 144
- 12.6 Analog Input 144
- Table 12−1.PGA Settings 145
- 12.8 Offset DAC 146
- 12.9 Modulator 146
- 12.10 Calibration 147
- 12.11 Digital Filter 148
- Digital Filter 149
- Analog-to-Digital Converter 149
- 12.11.1 Multiplexing Channels 150
- Table 12−3.Filter Settling 150
- 12.12 Voltage Reference 151
- 7 6 5 4 3 2 1 0 Reset Value 152
- 12.13.1 Manual Summation Mode 154
- 12.13.2 ADC Summation Mode 154
- Summation/Shifter Register 155
- Figure 12−6. Circuit Drawing 160
- 12.16.1 Differential V 161
- Chapter 13 163
- 13.1 Description 164
- 13.2 Functional Description 164
- Functional Description 165
- 13.4 SPI Signals 167
- 13.5 SPI System Errors 168
- 13.6 Data Transfers 169
- Data Transfers 170
- 13.7 FIFO Operation 171
- 13.8 Code Examples 172
- # -% 175
- 14.1 Description 176
- 14.2 Low-Voltage Detect 176
- 14.2.1 Power Supply 177
- 14.3 Watchdog Timer 178
- WDTCON = 0x80; // Set EWDT 179
- Watchdog Timer 181
- Additional MSC1210 Hardware 181
- #+ 183
- 15.1 Hardware Configuration 184
- CADDR 7F 185
- Hardware Configuration 186
- 15.2 Advanced Flash Memory 188
- 15.3 Breakpoint Generator 189
- 15.3.3 Disabling a Breakpoint 190
- 15.4 Power Optimization 191
- ./0#01 195
- 16.1 Description 196
- 16.2 Syntax 196
- 16.3 Number Bases 198
- 16.4 Expressions 198
- 16.5 Operator Precedence 199
- 8052 Assembly Language 201
- Register Assignment (MOV) 202
- MOV R2,R1 ;INVALID!! 203
- MOV @R0,@R1 ;INVALID!! 203
- 16.11 Program Loops (DJNZ) 206
- 16.14 Value Comparison (CJNE) 210
- MOV B,#75h ;Load B with 75h 215
- MUL AB ;Multiply A by B 215
- MOV B,#13h ;Load B with 13h 216
- DIV AB ;Divide A by B 216
- Table 16−2.Results of ANL 218
- Table 16−3.Results of ORL 218
- Table 16−4.Results of XRL 218
- ;table we want to read 226
- ;RET instruction 227
- RET ;Return from subroutine 227
- 2 229
- 17.1 Description 230
- Description 231
- Keil Simulator 231
- 17.2 Timers 232
- Figure 17−2. Timer/Counter 0 233
- Figure 17−5. Interrupt System 234
- 17.3 Timer 2 239
- 17.4 Watchdog Timer 240
- 17.5 System Timer 244
- 17.6 Clock Control 244
- Figure 17−9. Error Message 247
- 17.8 Summation/Shifter 248
- Summation/Shifter 249
- 17.9 Interrupts 258
- 17.10 Ports 259
- 17.11.1 SPI Sample Code 262
- Figure 17−17. Keil Debugger 267
- 17.13 Serial Port I/O 268
- Serial Port I/O 269
- 17.14 Additional Resource 274
- 000./ 275
- 300* 277
- "00 279
- C.1 Description 280
- Boot ROM Routines 281
- Appendix D 283
- ./00 285
- E.1 Description 286
- E.2 8052 Instruction Set 287
- ANL Bitwise AND 290
- Compare and Jump if Not Equal 291
- CLR Clear Register 291
- CPL Complement Register 292
- DA Decimal Adjust Accumulator 292
- DEC Decrement Register 293
- DIV Divide Accumulator by B 293
- INC Increment Reister 295
- JB Jump if Bit Set 296
- JC Jump if Carry Set 296
- JNB Jump if Bit Not Set 297
- JNC Jump if Carry Not Set 297
- JZ Jump if Accumulator Zero 298
- LCALL Long Call 298
- LJMP Long Jump 298
- MOV DPTR Move value into DPTR 301
- MUL Multiply Accumulator by B 302
- NOP No Operation 302
- ORL Bitwise OR 303
- POP Pop Value from Stack 304
- PUSH Push Value onto Stack 304
- RET Return from Subroutine 305
- RETI Return from Interrupt 305
- RL Rotate Accumulator Left 305
- RR Rotate Accumulator Right 306
- SETB Set Bit 306
- SJMP Short Jump 307
- XCH Exchange Bytes 308
- XCHD Exchange Digit 308
- XRL Bitwise Exclusive OR 309
- 8052 Instruction Set 310
- ??? 0xA5 1 1 C 310
- Appendix F 311
- Interrupt Enable (IE) 313
- INTERRUPT PRIORITY (IP) 314
- Port 0 (P0) 314
- Port 1 (P1) 315
- Port 2 (P2) 315
- Port 3 (P3) 316
- Program Status Word (PSW) 317
- Serial Control (SCON) 318
- Timer Control (TCON) 319
- Timer 2 Control (T2CON) 320
- ! 321
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