Texas-instruments TMS320DM644x Manuale Utente

TMS320DM644x DMSoCGeneral-Purpose Input/Output (GPIO)User's GuideLiterature Number: SPRUE25December 2005

www.ti.com2.3 GPIO Register StructurePeripheral ArchitectureThe GPIO signals are grouped into banks of 16 signals per bank.The GPIO configuration regi

www.ti.com2.4 Using a GPIO Signal as an OutputPeripheral ArchitectureTable 1. GPIO Register Bits and Banks Associated With GPIO Pins (continued)GPIO S

www.ti.com2.5 Using a GPIO Signal as an InputPeripheral Architecture2.4.2 Controlling the GPIO Output Signal StateThere are three registers that contr

www.ti.com2.6 Reset Considerations2.7 Interrupt SupportPeripheral ArchitectureThe GPIO peripheral has two reset sources: software reset and hardware r

www.ti.comPeripheral Architecture2.7.3 Configuring GPIO Interrupt Edge TriggeringEach GPIO interrupt source can be configured to generate an interrupt

www.ti.com2.8 EDMA Event Support2.9 Power Management2.10 Emulation ConsiderationsPeripheral ArchitectureThe GPIO peripheral can provide synchronizatio

www.ti.com3 RegistersRegistersTable 4 lists the memory-mapped registers for the general-purpose input/output (GPIO). See thedevice-specific data manua

www.ti.com3.1 Peripheral Identification Register (PID)RegistersThe peripheral identification register (PID) contains identification data (type, class,

www.ti.com3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN)RegistersThe GPIO interrupt per-bank enable register (BINTEN) is shown in Figure 3 and d

www.ti.com3.3 GPIO Direction Registers (DIR n)RegistersThe GPIO direction register (DIR n) determines if GPIO pin n in GPIO bank I is an input or an o

2 SPRUE25 – December 2005

www.ti.com3.4 GPIO Output Data Register (OUT_DATA n)RegistersThe GPIO output data register (OUT_DATA n) determines the value driven on the correspondi

www.ti.com3.5 GPIO Set Data Register (SET_DATA n)RegistersThe GPIO set data register (SET_DATA n) controls driving high the corresponding GPIO pin n i

www.ti.comRegistersTable 9. GPIO Set Data Register (SET_DATA n) Field DescriptionsBit Field Value Description31-16 SET n Set output drive state of GPI

www.ti.com3.6 GPIO Clear Data Register (CLR_DATA n)RegistersThe GPIO clear data register (CLR_DATA n) controls driving low the corresponding GPIO pin

www.ti.comRegistersTable 10. GPIO Clear Data Register (CLR_DATA n) Field DescriptionsBit Field Value Description31-16 CLR n Clear output drive state o

www.ti.com3.7 GPIO Input Data Register (IN_DATA n)RegistersThe current state of the GPIO signals is read using the GPIO input data register (IN_DATA n

www.ti.com3.8 GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIG n)RegistersThe GPIO set rising edge interrupt register (SET_RIS_TRIG n) enables a

www.ti.comRegistersFigure 21. GPIO Bank 4 Set Rising Edge Interrupt Register (SET_RIS_TRIG4)31 16ReservedR-015 8ReservedR-07 6 5 4 3 2 1 0Reserved SET

www.ti.com3.9 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIG n)RegistersThe GPIO clear rising edge interrupt register (CLR_RIS_TRIG n) disabl

www.ti.comRegistersFigure 24. GPIO Bank 4 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG4)31 16ReservedR-015 8ReservedR-07 6 5 4 3 2 1 0Reserved C

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www.ti.com3.10 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIG n)RegistersThe GPIO set falling edge interrupt register (SET_FAL_TRIG n) enables

www.ti.comRegistersFigure 27. GPIO Bank 4 Set Falling Edge Interrupt Register (SET_FAL_TRIG4)31 16ReservedR-015 8ReservedR-07 6 5 4 3 2 1 0Reserved SE

www.ti.com3.11 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIG n)RegistersThe GPIO clear falling edge interrupt register (CLR_FAL_TRIG n) dis

www.ti.comRegistersFigure 30. GPIO Bank 4 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG4)31 16ReservedR-015 8ReservedR-07 6 5 4 3 2 1 0Reserved

www.ti.com3.12 GPIO Interrupt Status Register (INTSTAT n)RegistersThe status of GPIO interrupt events can be monitored by reading the GPIO interrupt s

www.ti.comRegistersFigure 33. GPIO Bank 4 Interrupt Status Register (INTSTAT4)31 16ReservedR-015 8ReservedR-07 6 5 4 3 2 1 0Reserved STAT70 STAT69 STA

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

List of Figures1 GPIO Peripheral Block Diagram ... 92 Peripher

List of Tables1 GPIO Register Bits and Banks Associated With GPIO Pins ... 102 GPIO Interrupts t

PrefaceSPRUE25 – December 2005Read This FirstAbout This ManualDescribes the general-purpose input/output (GPIO) peripheral in the TMS320DM644x Digital

www.ti.comRelated Documentation From Texas InstrumentsSPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal pr

1 Introduction1.1 Purpose of the Peripheral1.2 FeaturesUser's GuideSPRUE25 – December 2005General-Purpose Input/Output (GPIO)The GPIO peripheral

www.ti.com1.3 Functional Block DiagramDIRregister logicDirectionregisterSET_DATACLR_DATAregisterOUTDATAregisterGPIOsignalSynchronizing flip−flopsINDAT