Texas-instruments TMS320C645x DSP Manuale Utente Pagina 133

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5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)
EMAC Port Registers
The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 75 and
described in Table 75 .
Figure 75. Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP)
31 16
RX nHDP
R/W-x
15 0
RX nHDP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset
Table 75. Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) Field Descriptions
Bit Field Value Description
31-0 RX nHDP Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor address
to this location allows receive DMA operations in the selected channel when a channel frame is
received. Writing to these locations when they are nonzero is an error (except at reset). Host
software must initialize these locations to zero on reset.
SPRU975B August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 133
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