Texas-instruments TMS320C3x Manuale Utente

TMS320C3xUser’s GuideLiterature Number: SPRU031E2558539-9761 revision LJuly 1997Printed on Recycled Paper

If You Need Assistancex If You Need Assistance . . .World-Wide Web SitesTI Online http://www.ti.comSemiconductor Product Information Center (PIC) http

Reset/Interrupt/Trap Vector Map 4-18Figure 4–10. Interrupt and Trap Vector Locations for TMS320C32EA (ITTP) + 3FhEA (ITTP) + 3EhEA (ITTP) + 3DhEA (ITT

Instruction Cache4-19Memory and the Instruction Cache4.3 Instruction CacheA 64 × 32-bit instruction cache speeds instruction fetches and lowers system

Instruction Cache 4-20Figure 4–12. Instruction-Cache ArchitectureSegment startaddress registersSegment wordsLRUStackSSA register 0Segment word 0Segmen

Instruction Cache4-21Memory and the Instruction Cache4.3.2 Instruction-Cache AlgorithmWhen the ’C3x requests an instruction word from external memory,

Instruction Cache 4-22Only instructions may be fetched from the program cache. All reads and writesof data in memory bypass the cache. Program fetches

Instructions may be fetched beforecache is enabledor frozen.Cache clearedInstructions may be fetched beforecache cleared.Instruction Cache4-23Memory a

5-1Data Formats and Floating-Point OperationIn the ’C3x architecture, data is organized into three fundamental types: integer,unsigned integer, and fl

Integer Formats 5-25.1 Integer FormatsThe ’C3x supports two integer formats: a 16-bit short-integer format and a32-bit single-precision integer format

Unsigned-Integer Formats5-3Data Formats and Floating-Point Operation5.2 Unsigned-Integer FormatsThe ’C3x supports two unsigned-integer formats: a 16-b

Floating-Point Formats 5-45.3 Floating-Point FormatsThe ’C3x supports four floating-point formats:A short floating-point format for immediate floating

If You Need Assistance / Trademarksxi Read This FirstDocumentationWhen making suggestions or reporting errors in documentation, please include the f

Floating-Point Formats5-5Data Formats and Floating-Point OperationThe exponent field is a 2s-complement number that determines the factor of 2by which

Floating-Point Formats 5-6The following examples illustrate the range and precision of the short floating-point format:Most positive:x = (2 – 2–11) ×

Floating-Point Formats5-7Data Formats and Floating-Point OperationThe following examples illustrate the range and precision of the ‘C32 shortfloating-

Floating-Point Formats 5-8You must use the following reserved values to represent 0 in the single-precisionfloating-point format:e= – 128s=0f=0The fol

Floating-Point Formats5-9Data Formats and Floating-Point OperationThe following examples illustrate the range and precision of the extended-precision

Floating-Point Formats 5-10Rewrite the mantissa as:Mantissa10.1 0 1 0 0 0 0 0 0 0 0Step 3: Shift the decimal point of the mantissa according to the va

Floating-Point Formats5-11Data Formats and Floating-Point OperationExample 5–2. Negative Number 0 1 C 0 0 0 0 0 Hex value0000 00

Floating-Point Formats 5-125.3.6 Conversion Between Floating-Point FormatsFloating-point operations assume several different formats for inputs and ou

Floating-Point Formats5-13Data Formats and Floating-Point OperationFigure 5–12. Converting from Single-Precision Floating-Point Format to Extended-Pre

Floating-Point Conversion (IEEE Std. 754) 5-145.4 Floating-Point Conversion (IEEE Std. 754)The ‘C3x floating-point format is not compatible with the I

ContentsxiiiContents1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Floating-Point Conversion (IEEE Std. 754)5-15Data Formats and Floating-Point OperationFigure 5–15. TMS320C3x Single-Precision 2s-Complement Floating-P

Floating-Point Conversion (IEEE Std. 754) 5-16Case 1 maps the IEEE positive NaNs and positive infinity to the single-preci-sion 2s-complement most pos

Floating-Point Conversion (IEEE Std. 754)5-17Data Formats and Floating-Point Operation5.4.1.1 IEEE-to-TMS320C3x Floating-Point Format ConversionExampl

Floating-Point Conversion (IEEE Std. 754) 5-18Example 5–4.IEEE-to-TMS320C3x Conversion (Fast Version) (Continued)* NOTE: SINCE THE STACK POINTER SP IS

Floating-Point Conversion (IEEE Std. 754)5-19Data Formats and Floating-Point OperationExample 5–5. IEEE-to-TMS320C3x Conversion (Complete Version)* TI

Floating-Point Conversion (IEEE Std. 754) 5-20Example 5–5.IEEE-to-TMS320C3x Conversion (Complete Version) (Continued)* HANDLE NaN AND INFINITYTSTB *+A

Floating-Point Conversion (IEEE Std. 754)5-21Data Formats and Floating-Point Operation5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format t

Floating-Point Conversion (IEEE Std. 754) 5-225.4.2.1 TMS320C3x-to-IEEE Floating-Point Format ConversionThe vast majority of the numbers represented b

Floating-Point Conversion (IEEE Std. 754)5-23Data Formats and Floating-Point OperationExample 5–6.TMS320C3x-to-IEEE Conversion (Fast Version) (Continu

Floating-Point Conversion (IEEE Std. 754) 5-24Example 5–7. TMS320C3x-to-IEEE Conversion (Complete Version)** TITLE TMS320C3x TO IEEE CONVERSION (COMPL

Contentsxiv 3 CPU Registers 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Floating-Point Conversion (IEEE Std. 754)5-25Data Formats and Floating-Point OperationExample 5–7.TMS320C3x-to-IEEE Conversion (Complete Version) (Con

Floating-Point Multiplication 5-265.5 Floating-Point MultiplicationA floating-point number α can be written in floating-point format as in the followi

Floating-Point Multiplication5-27Data Formats and Floating-Point OperationIf c(exp) has overflowed (step 11) in the positive direction, then step 14se

Floating-Point Multiplication 5-28Figure 5–16. Flowchart for Floating-Point Multiplicationα(man)b(man) α(exp)b(exp)(1) (2)Multiply mantissas Add expon

Floating-Point Multiplication5-29Data Formats and Floating-Point OperationExample 5–8 through Example 5–12 illustrate how floating-point multiplicatio

Floating-Point Multiplication 5-30Example 5–9. Floating-Point Multiply (Both Mantissas = 1.5)Let:α = 1.5 × 2α(exp)= 01.0000000000000000000000 × 2α(

Floating-Point Multiplication5-31Data Formats and Floating-Point OperationExample 5–11. Floating-Point Multiply Between Positive and Negative Numbers

Floating-Point Addition and Subtraction 5-325.6 Floating-Point Addition and SubtractionIn floating-point addition and subtraction, two floating-point

Floating-Point Addition and Subtraction5-33Data Formats and Floating-Point OperationFigure 5–17. Flowchart for Floating-Point Additionα(man)b(man) α(e

Floating-Point Addition and Subtraction 5-34The following examples describe the floating-point addition and subtractionoperations. It is assumed that

Contentsxv Contents5.3.3 Single-Precision Floating-Point Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Extended-

Floating-Point Addition and Subtraction5-35Data Formats and Floating-Point OperationExample 5–14. Floating-Point SubtractionA subtraction is performe

Floating-Point Addition and Subtraction 5-36Example 5–16. Floating-Point Addition/Subtraction With Floating-Point 0When floating-point addition and s

Normalization Using the NORM Instruction5-37Data Formats and Floating-Point Operation5.7 Normalization Using the NORM InstructionThe NORM instruction

Normalization Using the NORM Instruction 5-38Figure 5–18. Flowchart for NORM Instruction OperationTest for special cases of c(man)c(exp) = –128(1)α(ma

Rounding (RND Instruction)5-39Data Formats and Floating-Point Operation5.8 Rounding (RND Instruction)The RND instruction rounds a number from the exte

Rounding (RND Instruction) 5-40Figure 5–19. Flowchart for Floating-Point Rounding by the RND InstructionTest for special cases of c(man)c(exp) = –128c

Floating-Point to Integer Conversion (FIX Instruction)5-41Data Formats and Floating-Point Operation5.9 Floating-Point to Integer Conversion (FIX Instr

Floating-Point to Integer Conversion (FIX Instruction) 5-42Figure 5–20. Flowchart for Floating-Point to Integer Conversion by FIX InstructionTest for

Integer to Floating-Point Conversion (FLOAT Instruction)5-43Data Formats and Floating-Point Operation5.10 Integer to Floating-Point Conversion (FLOAT

Fast Logarithms on a Floating-Point Device 5-445.11 Fast Logarithms on a Floating-Point DeviceThe following TMS320C30/C40 function calculates the log

Contentsxvi 7.1.4 RPTS Instruction 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5 Re

Fast Logarithms on a Floating-Point Device5-45Data Formats and Floating-Point OperationN * log2(mant_old) = EXP_new + log2(mant_new)log2(mant_old) = E

Fast Logarithms on a Floating-Point Device 5-46are equivalent to the seven MSBs of the logarithm. If the exponent could holdall the bits needed for fu

Fast Logarithms on a Floating-Point Device5-47Data Formats and Floating-Point OperationWhen finished, the bits representing the finished logarithm are

Fast Logarithms on a Floating-Point Device 5-48Figure 5–23. Fast Logarithm for FFT Displays***********************************************************

6-1Addressing ModesThe ’C3x supports five groups of powerful addressing modes. Six types ofaddressing that allow data access from memory, registers, a

Addressing Types 6-26.1 Addressing TypesYou can access data from memory, registers, and the instruction word by usingfive types of addressing:Register

Register Addressing6-3Addressing Modes6.2 Register AddressingIn register addressing, a CPU register contains the operand, as shown in thisexample: AB

Direct Addressing 6-46.3 Direct AddressingIn direct addressing, the data address is formed by the concatenation of theeight LSBs of the data-page poin

Indirect Addressing6-5Addressing Modes6.4 Indirect AddressingIndirect addressing specifies the address of an operand in memory through thecontents of

Indirect Addressing 6-6Figure 6–2. Indirect Addressing Operand EncodingLSBMSB5 bitsmod ARn disp3 bits 0, 5, or 8 bitsNote: Auxiliary RegisterThe auxil

Contentsxvii Contents9 TMS320C30 and TMS320C31 External-Memory Interface 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of p

Indirect Addressing6-7Addressing ModesTable 6–2. Indirect Addressing(a) Indirect addressing with displacementMod Field Syntax Operation Description000

Indirect Addressing 6-8Table 6–2. Indirect Addressing (Continued)(c) Indirect addressing with index register IR1Mod Field Syntax Operation Description

Indirect Addressing6-9Addressing ModesExample 6–3. Indirect Addressing With Predisplacement AddThe address of the operand to fetch is the sum of an au

Indirect Addressing 6-10Example 6–5. Indirect Addressing With Predisplacement Add and ModifyThe address of the operand to fetch is the sum of an auxil

Indirect Addressing6-11Addressing ModesExample 6–7. Indirect Addressing With Postdisplacement Add and ModifyThe address of the operand to fetch is the

Indirect Addressing 6-12Example 6–9. Indirect Addressing With Postdisplacement Add and Circular ModifyThe address of the operand to fetch is the conte

Indirect Addressing6-13Addressing ModesExample 6–11. Indirect Addressing With Preindex AddThe address of the operand to fetch is the sum of an auxilia

Indirect Addressing 6-14Example 6–13. Indirect Addressing With Preindex Add and ModifyThe address of the operand to fetch is the sum of an auxiliary r

Indirect Addressing6-15Addressing ModesExample 6–15. Indirect Addressing With Postindex Add and ModifyThe address of the operand to fetch is the conte

Indirect Addressing 6-16Example 6–17. Indirect Addressing With Postindex Add and Circular ModifyThe address of the operand to fetch is the contents of

Contentsxviii 11.1.3 TMS320C31 Boot-Loading Sequence 11-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 TMS320C31 Boot Data St

Indirect Addressing6-17Addressing ModesExample 6–19. Indirect Addressing With Postindex Add and Bit-Reversed ModifyThe address of the operand to fetch

Immediate Addressing 6-186.5 Immediate AddressingIn immediate addressing, the operand is a 16-bit (short) or 24-bit (long) immediatevalue contained in

PC-Relative Addressing6-19Addressing Modes6.6 PC-Relative AddressingProgram counter (PC)-relative addressing is used for branching. It adds thecontent

PC-Relative Addressing 6-20Figure 6–3. Encoding for 24-Bit PC-Relative Addressing Mode(a) BR, BRD: unconditional branches (standard and delayed)31 25

Circular Addressing6-21Addressing Modes6.7 Circular AddressingMany DSP algorithms, such as convolution and correlation, require a circularbuffer in me

Circular Addressing 6-22Figure 6–6. Logical and Physical Representation of Circular Buffer after Writing Eight ValuesStart Enda) Logical representatio

Circular Addressing6-23Addressing ModesIn circular addressing, index refers to the K LSBs (from the K-bit boundary criteria)of the auxiliary register

Circular Addressing 6-24Example 6–24. Circular Addressing*AR0++(5)% ; AR0 = 0 (0 value)*AR0++(2)% ; AR0 = 5 (1st value)*AR0– –(3)% ; AR0 = 1 (2nd valu

Circular Addressing6-25Addressing ModesExample 6–25. FIR Filter Code Using Circular Addressing* Impulse Response.sect ”Impulse_Resp”H .float 1.0.float

Bit-Reversed Addressing 6-266.8 Bit-Reversed AddressingThe ’C3x can implement fast Fourier transforms (FFT) with bit-reversed ad-dressing. Whenever da

Contentsxix Contents12.3.5 TMS320C32 DMA Internal Priority Schemes 12-62. . . . . . . . . . . . . . . . . . . . . . . . . 12.3.6 CPU and DMA Control

Bit-Reversed Addressing6-27Addressing ModesExample 6–26. Bit-Reversed Addressing*AR2++(IR0)B ; AR2= 0110 0000 (0th value)*AR2++(IR0)B ; AR2= 0110 1000

Aligning Buffers With the TMS320 Floating-Point DSP Assembly 6-286.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language ToolsTo ali

System and User Stack Management6-29Addressing Modes6.10 System and User Stack ManagementThe ’C3x provides a dedicated system-stack pointer (SP) for b

System and User Stack Management 6-306.10.2 StacksStacks can be built from low to high memory or high to low memory. Two casesfor each type of stack a

System and User Stack Management6-31Addressing ModesFigure 6–11.Implementations of Low-to-High Memory StacksTop of stackLow memoryHigh memory(Free)Bot

7-1Program Flow ControlThe TMS320C3x provides a complete set of constructs that facilitate softwareand hardware control of the program flow. Software

Repeat Modes 7-27.1 Repeat ModesThe repeat modes of the ’C3x can implement zero-overhead looping. For manyalgorithms, most execution time is spent in

Repeat Modes7-3Program Flow Control7.1.1 Repeat-Mode Control BitsTwo bits are important to the operation of RPTB and RPTS:RM bit. The repeat-mode (RM)

Repeat Modes 7-4Example 7–1. Repeat-Mode Control Algorithmif RM == 1 ; If in repeat mode (RPTB or RPTS)if S == 1 ; If RPTSif first time through ; If t

Repeat Modes7-5Program Flow ControlAll block repeats initiated by RPTB can be interrupted. When RPTB src(source) instruction executes, it performs the

Figuresxx Figures1–1 TMS320C3x Devices Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 TM

Repeat Modes 7-6The RPTS instruction loads all registers and mode bits necessary for the opera-tion of the single-instruction repeat mode. Step 1 load

Repeat Modes7-7Program Flow ControlExample 7–4. Incorrectly Placed Delayed BranchLDI 15,RC ; Load repeat counter with 15RPTB ENDLOOP ; Execute block o

Repeat Modes 7-87.1.7 Nested Block RepeatsBlock repeats (RPTB) can be nested. Since the registers RS, RE, RC, andST control the repeat-mode status, th

Delayed Branches7-9Program Flow Control7.2 Delayed BranchesThe ’C3x offers three main types of branching: standard, delayed, and condi-tional delayed.

Delayed Branches 7-10Example 7–6. Incorrectly Placed Delayed BranchesB1: BD L1NOPNOPB2: B L2 ; This branch is incorrectly placed.NOPNOPNOP...For faste

Calls, Traps, and Returns7-11Program Flow Control7.3 Calls, Traps, and ReturnsCalls and traps provide a means of executing a subroutine or function wh

Calls, Traps, and Returns 7-12RETIcond returns from traps or calls like the RETScond, with the additionthat RETIcond also sets the GIE bit of the stat

Interlocked Operations7-13Program Flow Control7.4 Interlocked OperationsOne of the most common parallel processing configurations is the sharing ofglo

Interlocked Operations 7-14The LDFI and LDII instructions perform the following actions:1) Simultaneously set XF0 to 0 and begin a read cycle. The tim

Interlocked Operations7-15Program Flow ControlNote: Timing Diagrams for SIGIThe timing diagrams for SIGI shown in the data sheets depict a zero waitst

IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service withou

Figuresxxi Contents5–1 Short-Integer Format and Sign-Extension of Short Integers 5-2. . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Single-Pre

Interlocked Operations 7-16Example 7–8 shows the implementation of a busy-waiting loop. If locationLOCK is the interlock for a critical section of cod

Interlocked Operations7-17Program Flow ControlFigure 7–2. Multiple TMS320C3xs Sharing Global MemoryGlobal memoryArbitration logic’C3x #2XF0 XF1Localme

Interlocked Operations 7-18The ’C3x code for V(S) is shown in Example 7–10; code for P(S) is shown inExample 7–11. Compare the code in Example 7–11 to

Interlocked Operations7-19Program Flow ControlExample 7–12. Code to Synchronize Two TMS320C3x Devices at the Software LevelNCode for ’C3x #2Code for ’

XF0 set as anoutput pin andXF1 set as aninput pinXF1 sampledXF0 driven lowand XF1 sampledXF0 pindriven highXF1 pinsampledXF0 pindriven lowInterlocked

Reset Operation7-21Program Flow Control7.5 Reset OperationThe ’C3x supports a nonmaskable external reset signal (RESET), which isused to perform syste

Reset Operation 7-22Table 7–3. TMS320C3x Pin Operation at Reset (Continued)DeviceSignal ‘C32‘C31‘C30Operation at ResetHOLDA Reset has no effectPRGW Re

Reset Operation7-23Program Flow ControlTable 7–3. TMS320C3x Pin Operation at Reset (Continued)DeviceSignal ‘C32‘C31‘C30Operation at ResetDR1 Asynchron

Reset Operation 7-24Table 7–3. TMS320C3x Pin Operation at Reset (Continued)DeviceSignal ‘C32‘C31‘C30Operation at ResetEmulation, Test, and ReservedEMU

Reset Operation7-25Program Flow ControlAt system reset, the following additional operations are performed:The peripherals are reset. This is a synchro

Figuresxxii 7–8 DMA Interrupt Processing 7-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupts 7-267.6 InterruptsThe ’C3x supports multiple internal and external interrupts, which can be used fora variety of applications. Internal int

Interrupts7-27Program Flow ControlTable 7–4. Reset, Interrupt, and Trap-Vector Locations for the TMS320C30/TMS320C31 Microprocessor ModeAddress Name F

Interrupts 7-28Table 7–5. Reset, Interrupt, and Trap-Branch Locations for the TMS320C31 Microcomputer Boot ModeAddress Name Function809FC1 INT0 Extern

Interrupts7-29Program Flow Control7.6.2 TMS320C32 Interrupt Vector TableSimilarly to the rest of the ’C3x device family, the ’C32’s reset vector locat

Interrupts 7-30Table 7–6. Interrupt and Trap-Vector Locations for the TMS320C32Address Name FunctionEA[ITTP] + 00h ReservedEA[ITTP] + 01h INT0 Externa

Interrupts7-31Program Flow Control7.6.3 Interrupt PrioritizationWhen two interrupts occur in the same clock cycle or when two previouslyreceived inter

Interrupts 7-327.6.4 CPU Interrupt Control BitsThree CPU registers contain bits that control interrupt operation:Status (ST) registerThe CPU global in

Interrupts7-33Program Flow ControlFigure 7–5. IF Register ModificationCorrect IncorrectLDI @MASK, R0 LDI IF, R1AND R0, IF AND @MASK, R1LDI R1, IFNote:

Interrupts 7-34Figure 7–6. CPU Interrupt ProcessingDMA proceeds according to SYNC bitsIf enabled,interrupt isa DMA interruptClear interrupt flagDMA co

Interrupts7-35Program Flow ControlIf you wish to make the interrupt service routine interruptible, you can set theGIE bit to 1 after entering the ISR.

Figuresxxiii Contents10–5 STRB1 Control Register 10-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupts 7-36Table 7–8. Interrupt LatencyCycle Description Fetch Decode Read Execute1 Recognize interrupt in single-cycle fetched(prog a + 1) instru

Interrupts7-37Program Flow ControlFigure 7–7. Interrupt Logic Functional DiagramINTnTocontrolsectionInternal interruptset signalInterruptflag (n)Inter

DMA Interrupts 7-387.7 DMA InterruptsInterrupts can also trigger DMA read and write operations. This is calledDMA synchronization. The DMA interrupt p

DMA Interrupts7-39Program Flow Control7.7.2 DMA Interrupt ProcessingFigure 7–8 shows the general flow of interrupt processing by the DMA coprocessor.F

DMA Interrupts 7-407.7.3 CPU/DMA InteractionIf the DMA is not using interrupts for synchronization of transfers, it is notaffected by the processing o

DMA Interrupts7-41Program Flow Control7.7.4 TMS320C3x Interrupt ConsiderationsGive careful consideration to ’C3x interrupts, especially if you make mo

DMA Interrupts 7-42Table 7–9. Pipeline Operation with PUSH STCycle Description Fetch Decode Read Execute1 NOP2 LDI NOP3 MPYI LDI NOP4 Read location V_

DMA Interrupts7-43Program Flow ControlOne solution is to use an instruction that is uninterruptible such as RPTS asfollows to set the GIE:RPTS 0AND 20

DMA Interrupts 7-447.7.5 TMS320C30 Interrupt ConsiderationsThe ’C30 silicon revisions earlier than 4.0 have two unique exceptions to theinterrupt oper

DMA Interrupts7-45Program Flow ControlInsert two NOP instructions immediately before the TRAPcond instruction.One NOP is insufficient in some cases, a

Figuresxxiv 11–5 Boot-Loader Serial-Port Load Flowchart 11-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6 Boot

DMA Interrupts 7-46ISR_n: PUSH ST ;PUSH DP ; Save registersPUSH R0 ;LDI 0, DP ; Clear Data-page PointerLDI @DUMMY_INT, R0 ; If DUMMY_INT is 0 or posit

Traps7-47Program Flow Control7.8 TrapsA trap is the equivalent of a software-triggered interrupt. In the ’C3x, traps andinterrupts are treated identic

Traps 7-48The RETIcond instruction manipulates the status flags as shown in block (3)in Figure 7–10. RETIcond provides a return from a trap or interru

Power Management Modes7-49Program Flow Control7.9 Power Management ModesThe following ’C3x devices have been enhanced by the addition of two power-dow

Power Management Modes 7-50The interrupt service routine (ISR) must have been set up before placingthe device in IDLE2 mode, because the instruction f

Power Management Modes7-51Program Flow ControlFigure 7–12. Interrupt Response Timing After IDLE2 Operation1st addressVector addressDataADDRINT0 FlagIN

Power Management Modes 7-52Figure 7–13. LOPOWER Timing32 CLKINH1H3CLKINLOPOWER readFigure 7–14. MAXSPEED TimingH1H3CLKINMAXSPEED read32 CLKIN

8-1Pipeline OperationPipeline OperationTwo characteristics of the’C3x that contribute to its high performance are:PipeliningConcurrent I/O and CPU op

PerfectoverlapPipeline Structure 8-28.1 Pipeline StructureThe following list describes the four major units of the ‘C3x pipeline structure andtheir fu

Pipeline Structure8-3Pipeline OperationFor ‘C30 and ‘C31, priorities from highest to lowest have been assigned toeach of the functional units of the p

Figuresxxv Contents12–41 TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register 12-60. . . . . . . . . . . . . . . 12–42 TMS320C32 CPU/DMA Interr

Pipeline Conflicts 8-48.2 Pipeline ConflictsPipeline conflicts in the ’C3x can be grouped into the following categories:Branch conflicts Branch confli

3PCFetch held fornew PC valuePipeline Conflicts8-5Pipeline OperationExample 8–1. Standard BranchBR THREE ; Unconditional branchMPYF ; Not executedADD

Noexecutedelay3PCPipeline Conflicts 8-6Example 8–2. Delayed BranchBRD THREE ; Unconditional delayed branchMPYF ; ExecutedADD ; ExecutedSUBF ; Executed

Decode/addressgeneration helduntil AR write iscompletedARs writtenPipeline Conflicts8-7Pipeline Operationis loaded, and a different auxiliary register

Decode/addressgeneration helduntil AR is readARs readPipeline Conflicts 8-8In Example 8–4, two auxiliary registers are added together, with the result

Pipeline Conflicts8-9Pipeline OperationMemory pipeline conflicts consist of the following four types:Program wait A program fetch is prevented from be

Fetch helduntil dataaccesscompletesData accessedPipeline Conflicts 8-10Example 8–5. Program Wait Until CPU Data Access CompletesADDF3 *AR0,*AR1,R0FIXM

2-cycle DMAaccessPipeline Conflicts8-11Pipeline OperationExample 8–6. Program Wait Due to Multicycle AccessADDF ; code in internal memoryMPY ; code in

1 wait staterequiredPipeline Conflicts 8-12Example 8–7. Multicycle Program Memory FetchesPipeline OperationPC FetchDecode Read Executen MPYF — — —n+1

Write mustcompletebefore thetwo reads cancomplete2 readsperformedPipeline Conflicts8-13Pipeline OperationExample 8–8. Single Store Followed by Two Rea

Tablesxxvi Tables1–1 TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison 1-5. . . . . . . . . . . . 1–2 Typical Applications of the TMS320 Fam

Read must wait until the writes arecompletedWrites performedPipeline Conflicts 8-14Example 8–9 shows a parallel store followed by a single load or rea

XF1 = 1,read must waitXF1 = 0,read operationis completePipeline Conflicts8-15Pipeline OperationExample 8–10. Interlocked LoadNOT R1,R0LDII 300h,AR2ADD

write access2-cycle external busPipeline Conflicts 8-16Example 8–11. Busy External PortSTF R0,@DMA1LDF @DMA2,R0Pipeline OperationPCFetch Decode Read E

2-cycle external busread accessPipeline Conflicts8-17Pipeline OperationExample 8–12. Multicycle Data ReadsLDF @DMA,R0Pipeline OperationPCFetch Decode

PC storecyclePipeline Conflicts 8-18Example 8–13. Conditional Calls and TrapsPipeline OperationPC FetchDecode Read Executen CALLcond———n+1 I CALLcond—

ARs readResolving Register Conflicts8-19Pipeline Operation8.3 Resolving Register ConflictsIf the auxiliary registers (AR7–AR0), the index registers (I

AR2 readAR2 writtenResolving Register Conflicts 8-20Example 8–15. Write to an AR Followed by an AR for Address Generation Without a Pipeline ConflictL

DP readDP writtenResolving Register Conflicts8-21Pipeline OperationExample 8–16. Write to DP Followed by a Direct Memory Read Without a Pipeline Confl

Memory Access for Maximum Performance 8-228.4 Memory Access for Maximum PerformanceIf program fetches and data accesses are performed so that the reso

Memory Access for Maximum Performance8-23Pipeline OperationTable 8–2. One Program Fetch and Two Data Accesses for Maximum PerformanceCase No.Primary B

Tablesxxvii Contents10–2 Data-Access Sequence for a Memory Configuration with Two Banks 10-14. . . . . . . . . . . . . . . 10–3 Wait-State Generatio

Clocking Memory Accesses 8-248.5 Clocking Memory AccessesThis section discusses the role of internal clock phases (H1 and H3) and howthe ’C3x handles

Clocking Memory Accesses8-25Pipeline OperationSee Chapter 6, Addressing Modes, for more information.As discussed in Chapter 7, the number of bus cycle

Clocking Memory Accesses 8-26If both source operands are to be fetched from memory, then memory readscan occur in several ways:If both operands are lo

2-cycle dummyload of src2R0, *AR6 until thestore is completeactual read ofsrc2 and src1Clocking Memory Accesses8-27Pipeline OperationExample 8–17. Dum

2-cycle storeThe read of src2 cannot startuntil the store is complete2-cycle read of src1 and src2Clocking Memory Accesses 8-28Example 8–18. Operand S

Clocking Memory Accesses8-29Pipeline Operation8.5.2.3 Operations with Parallel StoresThe next class of instructions includes every instruction that ha

Clocking Memory Accesses 8-30If dst1 and dst2 are both written to external memory, a single CPU cycleis still all that is necessary to complete the st

9-1TMS320C30 and TMS320C31External-Memory InterfaceThis chapter describes the ’C30 and ’C31 external-memory interface. SeeChapter 10, Enhanced Externa

Overview 9-29.1 OverviewThe ’C30 provides two external interfaces: the primary bus and the expansionbus. The TMS320C31 provides one external interface

Memory Interface Signals9-3TMS320C30 and TMS320C31 External-Memory Interface9.2 Memory Interface SignalsThis section describes the differences between

Examplesxxviii Examples4–1 Pipeline Effects of Modifying the Cache Control Bits 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Po

Memory Interface Signals 9-4Table 9–1. Primary Bus Interface SignalsSignal Type†DescriptionValueAfter ResetIdle StatusSTRB O/Z Primary interface acces

Memory Interface Signals9-5TMS320C30 and TMS320C31 External-Memory InterfaceTable 9–2. Expansion Bus Interface SignalsSignal Type†DescriptionValueAfte

Memory Interface Signals 9-6Figure 9–1. Memory-Mapped External Interface Control RegistersExpansion-bus control (’C30 only)808060h808061h808062h808063

Memory Interface Control Registers9-7TMS320C30 and TMS320C31 External-Memory Interface9.3 Memory Interface Control RegistersTwo memory interface contr

Memory Interface Control Registers 9-8Table 9–3. Primary-Bus Control Register BitsAbbreviation Reset Value Name DescriptionHOLDST 0 Hold status bit Th

Memory Interface Control Registers9-9TMS320C30 and TMS320C31 External-Memory Interface9.3.2 Expansion-Bus Control RegisterThe expansion-bus control re

Programmable Wait States 9-109.4 Programmable Wait StatesThe ’C3x has its own internal software-configurable ready-generation capabilityfor each strob

Programmable Wait States9-11TMS320C30 and TMS320C31 External-Memory InterfaceTable 9–5. Wait-State GenerationInputs OutputSWW Bit Field /RDYext /RDYwt

Programmable Bank Switching 9-129.5 Programmable Bank SwitchingProgrammable bank switching allows you to switch between external memorybanks without h

Programmable Bank Switching9-13TMS320C30 and TMS320C31 External-Memory InterfaceThe ’C3x has an internal register that contains the MSBs (as defined b

Examplesxxix Contents6–19 Indirect Addressing With Postindex Add and Bit-Reversed Modify 6-17. . . . . . . . . . . . . . . . . . 6–20 Short-Immediat

Programmable Bank Switching 9-14Figure 9–5. Bank-Switching ExampleH3H1STRBR/WADRDYRead Read ReadExtracycleNote:After changing BNKCMP, up to three inst

External Memory Interface Timing9-15TMS320C30 and TMS320C31 External-Memory Interface9.6 External Memory Interface TimingThis section discusses functi

External Memory Interface Timing 9-16The (M)STRB signal is low for the active portion of both reads and writes. Theactive portion lasts one H1 cycle.

External Memory Interface Timing9-17TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–6. Read-Read-Write for (M)STRB = 0H3H1(M)STRB(X)R/W(X)A(

External Memory Interface Timing 9-18Figure 9–7 illustrates a write-write-read sequence for (M)STRB active and nowait states. The address and data wri

External Memory Interface Timing9-19TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–8 illustrates a read cycle with one wait state. Since (X

External Memory Interface Timing 9-20Figure 9–9 illustrates a write cycle with one wait state. Since initially (X)RDY = 1,the write cycle is extended.

External Memory Interface Timing9-21TMS320C30 and TMS320C31 External-Memory Interface9.6.2 Expansion-Bus I/O CyclesIn contrast to primary bus and MSTR

External Memory Interface Timing 9-22Figure 9–11 illustrates a read with one wait state when IOSTRB is active, andFigure 9–12 illustrates a write with

External Memory Interface Timing9-23TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–12. Write With One Wait State for IOSTRB = 0H3H1XAXDXR/W

Examplesxxx 12–3 Serial-Port Register Setup #1 12-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Memory Interface Timing 9-24Figure 9–13 through Figure 9–23 illustrate the various transitions betweenmemory reads and writes, and I/O writes

External Memory Interface Timing9-25TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–14. Memory Read and I/O Read for Expansion BusXRDYXDXAXR

External Memory Interface Timing 9-26Figure 9–15. Memory Write and I/O Write for Expansion BusH3H1XAXDXRDYMSTRBIOSTRBXR/WMemory address I/O addressI/O

External Memory Interface Timing9-27TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–16. Memory Write and I/O Read for Expansion BusH3H1XAXDX

External Memory Interface Timing 9-28Figure 9–17. I/O Write and Memory Write for Expansion BusH3H1XAXDXRDYMSTRBIOSTRBXR/WI/O address Memory addressI/O

External Memory Interface Timing9-29TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–18. I/O Write and Memory Read for Expansion BusH3H1XAXDX

External Memory Interface Timing 9-30Figure 9–19. I/O Read and Memory Write for Expansion BusI/O address Memory addressMemory writeXRDYXDXAXR/WIOSTRBM

External Memory Interface Timing9-31TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–20. I/O Read and Memory Read for Expansion BusMemory add

External Memory Interface Timing 9-32Figure 9–21. I/O Write and I/O Read for Expansion BusI/O writeXRDYXDXAXR/WIOSTRBMSTRBH1H3I/O readI/O address I/O

External Memory Interface Timing9-33TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–22. I/O Write and I/O Write for Expansion BusI/O writeI/

iii PrefaceRead This FirstAbout This ManualThis user’s guide serves as an applications reference book for the TMS320C3xgeneration of digital signal p

1-1IntroductionThe TMS320C3x generation of digital signal processors (DSPs) are high-performance CMOS 32-bit floating-point devices in the TMS320 fami

External Memory Interface Timing 9-34Figure 9–23. I/O Read and I/O Read for Expansion BusI/O readI/O readXRDYXDXAXR/WIOSTRBMSTRBH1H3I/O address I/O ad

External Memory Interface Timing9-35TMS320C30 and TMS320C31 External-Memory InterfaceFigure 9–24 and Figure 9–25 illustrate the signal states when a b

External Memory Interface Timing 9-36Figure 9–25. Inactive Bus States for STRB and MSTRBH3H1(X)A(X)D(X)R/W(M)STRB(X)RDYWrite data(X)RDY ignoredBus ina

External Memory Interface Timing9-37TMS320C30 and TMS320C31 External-Memory Interface9.6.3 Hold CyclesFigure 9–26 illustrates the timing for HOLD and

10-1TMS320C32 Enhanced External MemoryInterfaceThe ’C32 external memory interface provides greater flexibility by improvingthe ’C3x core with several

TMS320C32 Memory Features 10-210.1 TMS320C32 Memory FeaturesThe ’C32 external memory interface includes the following features:One external pin, PRGW,

TMS320C32 Memory Overview10-3TMS320C32 Enhanced External Memory Interface10.2 TMS320C32 Memory OverviewThe following sections describe examples, contr

TMS320C32 Memory Overview 10-4IOSTRB can access 32-bit data from 32-bit wide memory. It does not have theflexibility of STRB0 and STRB1 since it is co

TMS320C32 Memory Overview10-5TMS320C32 Enhanced External Memory InterfaceThe PRGW status bit field of the CPU status (ST) register reflects the settin

TMS320C32 Memory Overview 10-610.2.3.2 16- or 32-Bit Floating-Point Data TypesThe ’C32 supports 16- or 32-bit floating point data. For 16-bit floating

TMS320C3x Devices 1-21.1 TMS320C3x DevicesThe ’C3x family consists of three members: the ’C30, ’C31, and ’C32. The’C30, ’C31, and ’C32 can perform par

Configuration10-7TMS320C32 Enhanced External Memory Interface10.3 ConfigurationTo access 8-, 16-, or 32-bit data (types) from 8-, 16-, or 32-bit wide

Configuration 10-810.3.1.1 STRB0 Control RegisterThe STRB0 control register (Figure 10–4) is a 32-bit register that contains thecontrol bits for the p

Configuration10-9TMS320C32 Enhanced External Memory InterfaceThe instruction immediately preceding a change in the data-size ormemory-width bit fields

Configuration 10-10Table 10–1 describes the bits in the STRBO, STRB1, and the IOSTRB controlregisters.Table 10–1. STRB0, STRB1, and IOSTRB Control Reg

Configuration10-11TMS320C32 Enhanced External Memory InterfaceTable 10–1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued)Abbreviation Descr

Configuration 10-12Table 10–1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued)Abbreviation DescriptionNameResetValueSign ext/zero-fill0 (ST

Configuration10-13TMS320C32 Enhanced External Memory InterfaceFigure 10–7. STRB ConfigurationSTRB0_BxSTRB1_BxSTRB0_BxSTRB configSTRB1_Bx10.3.2 Using P

Configuration 10-14By setting the bit fields of the STRB0 bus control register with a physical-memory width of 32 bits and a data type size of 32 bits

Programmable Wait States10-15TMS320C32 Enhanced External Memory Interface10.4 Programmable Wait StatesThe ’C3x has its own internal software-configura

Programmable Wait States 10-16Table 10–3. Wait-State GenerationInputs OutputSWW BitField/RDYext/RDYwtcnt /RDYint Functional Description0001xx01Wait un

TMS320C3x Devices1-3IntroductionFigure 1–1. TMS320C3x Devices Block DiagramPrimary portmemory interfaceData access32-bit (’C30-’C31)8/16/32-bit (’C32)

Programmable Bank Switching10-17TMS320C32 Enhanced External Memory Interface10.5 Programmable Bank SwitchingProgrammable bank switching allows you to

Programmable Bank Switching 10-18The ’C3x has an internal register that contains the MSBs (as defined by theBNKCMP field) of the last address used for

Programmable Bank Switching10-19TMS320C32 Enhanced External Memory InterfaceNote:After changing BNKCMP, up to three instructions are fetched before th

32-Bit-Wide Memory Interface 10-2010.6 32-Bit-Wide Memory InterfaceThe ’C32 memory interface to 32-bit-wide external memory uses STRBx_B3through STRBx

32-Bit-Wide Memory Interface10-21TMS320C32 Enhanced External Memory InterfaceTable 10–5. Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-Typ

32-Bit-Wide Memory Interface 10-22For example, reading from or writing to memory locations 904000h to904004h involves the pins listed in Table 10–6.Ta

32-Bit-Wide Memory Interface10-23TMS320C32 Enhanced External Memory InterfaceFigure 10–12. Functional Diagram for 16-Bit Data-Type Size and 32-Bit Ext

32-Bit-Wide Memory Interface 10-24Case 3: 32-Bit-Wide Memory With 32-Bit Data-Type SizeWhen the data size is 32 bits, the ’C32 does not shift the inte

32-Bit-Wide Memory Interface10-25TMS320C32 Enhanced External Memory InterfaceFor example, reading or writing to memory locations 904000h to 904004hinv

16-Bit-Wide Memory Interface 10-2610.7 16-Bit-Wide Memory InterfaceThe ’C32 memory interface to 16-bit-wide external memory uses STRBx_B3 pinas an add

TMS320C3x Devices 1-41.1.4 TMS320C32The ’C32 is the newest member of the ’C3x generation. They are enhancedversions of the ’C3x family and the lowest

16-Bit-Wide Memory Interface10-27TMS320C32 Enhanced External Memory InterfaceTable 10–10. Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bi

16-Bit-Wide Memory Interface 10-28Table 10–11. Example of 8-Bit Data-Type Size and 16-Bit-Wide External MemoryInternal Address BusExternal Address Pin

16-Bit-Wide Memory Interface10-29TMS320C32 Enhanced External Memory InterfaceFigure 10–16. Functional Diagram for 16-Bit Data-Type Size and 16-Bit Ext

16-Bit-Wide Memory Interface 10-30Case 6: 16-Bit-Wide Memory with 32-Bit Data-Type SizeWhen the data type size is 32 bits, the ’C32 does not shift the

16-Bit-Wide Memory Interface10-31TMS320C32 Enhanced External Memory InterfaceTable 10–13. Example of 16-Bit-Wide Memory With 32-Bit Data-Type SizeInte

8-Bit-Wide Memory Interface 10-3210.8 8-Bit-Wide Memory Interface’C32 memory interface to an 8-bit wide external memory uses STRBx_B3 andSTRBx_B2 pins

8-Bit-Wide Memory Interface10-33TMS320C32 Enhanced External Memory InterfaceFigure 10–19. Functional Diagram for 8-Bit Data-Type Size and 8-Bit Extern

8-Bit-Wide Memory Interface 10-34Case 8: 8-Bit Wide Memory With 16-Bit Data-Type SizeWhen the data-type size is 16 bits, the ‘C32 shifts the internal

8-Bit-Wide Memory Interface10-35TMS320C32 Enhanced External Memory InterfaceFor example, reading or writing to memory locations A04000h to A04002hinvo

8-Bit-Wide Memory Interface 10-36Figure 10–21. Functional Diagram for 32-Bit Data-Type Size and 8-Bit External-MemoryWidthA24A23A22.A4A2A1A0CSI/O(7–0)

TMS320C3x Devices1-5IntroductionTable 1–1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison Memory (words)CycleOn-Chip Off-Chip PeripheralsD

8-Bit-Wide Memory Interface10-37TMS320C32 Enhanced External Memory InterfaceFor example, reading or writing to memory locations A04000h to A04001hinvo

External Ready Timing Improvement 10-3810.9 External Ready Timing ImprovementThe ready (RDY) timing should relate to the H1 low signal as shown inFigu

Bus Timing10-39TMS320C32 Enhanced External Memory Interface10.10 Bus TimingThis section discusses functional timing of operations on the external memo

Bus Timing 10-40Figure 10–23. Read-Read-Write Sequence for STRBx ActiveRDYDAR/WSTRBxH1H3Read Read WriteFigure 10–24 shows a zero wait-state write-writ

Bus Timing10-41TMS320C32 Enhanced External Memory InterfaceFigure 10–25 shows a one wait-state read sequence and Figure 10–26 showsthe write sequence

Bus Timing 10-42Figure 10–26. One Wait-State Write Sequence for STRBx ActiveRDYDAR/WSTRBxH1H3Extra cycleWrite10.10.2 IOSTRB Bus CyclesIn contrast to S

Bus Timing10-43TMS320C32 Enhanced External Memory InterfaceFigure 10–27 illustrates a zero wait-state read and write sequence for IOSTRBactive. During

Bus Timing 10-44Figure 10–28. One Wait-State Read Sequence for IOSTRB ActiveIOSTRBRDYDAR/WH1H3Extra cycleReadFigure 10–29. One Wait-State Write Sequen

Bus Timing10-45TMS320C32 Enhanced External Memory InterfaceFigure 10–30. STRBx Read and IOSTRB WriteI/O WriteReadSTRB0,1IOSTRBRDYDAR/WH1H3Figure 10–31

Bus Timing 10-46Figure 10–32 and Figure 10–33 illustrate the transitions between STRBxwrites and IOSTRB writes and reads, respectively. In these trans

TMS320C3x Devices1-6Table 1–1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison (Continued)Memory (words)CycleOn-Chip Off-ChipPeripheralsDev

Bus Timing10-47TMS320C32 Enhanced External Memory InterfaceFigure 10–34 through Figure 10–37 show the transitions between IOSTRBwrites/reads and STRBx

Bus Timing 10-48Figure 10–35. IOSTRB Write and STRBx ReadI/O Write ReadSTRBxIOSTRBRDYDAR/WH1H3Figure 10–36. IOSTRB Read and STRBx WriteI/O read WriteS

Bus Timing10-49TMS320C32 Enhanced External Memory InterfaceFigure 10–37. IOSTRB Read and STRBx ReadReadI/O ReadSTRBxIOSTRBRDYDAR/WH1H3Figure 10–38 thr

Bus Timing 10-50Figure 10–38. IOSTRB Write and ReadI/O writeIOSTRBRDYDAR/WH1H3I/O readFigure 10–39. IOSTRB Write and WriteI/O writeI/O writeIOSTRBRDYD

Bus Timing10-51TMS320C32 Enhanced External Memory InterfaceFigure 10–40. IOSTRB Read and ReadI/O ReadI/O ReadIOSTRBRDYDAR/WH1H310.10.3 Inactive Bus St

Bus Timing 10-52Figure 10–42. Inactive Bus States Following STRBx Bus CycleI/O writeSTRBxRDYDAR/WH1H3Bus inactive RDY ignored

11-1Using the TMS320C31 andTMS320C32 Boot LoadersThe ’C31 and ’C32 have on-chip boot loaders that can load and execute pro-grams received from a host

TMS320C31 Boot Loader 11-211.1 TMS320C31 Boot LoaderThis section describes how to use the ’C31 microcomputer/boot loader (MCBL/MP) function. This feat

TMS320C31 Boot Loader11-3Using the TMS320C31 and TMS320C32 Boot LoadersTable 11–1. Boot-Loader Mode SelectionINT0 INT1 INT2 INT3 Loader Mode Memory Ad

TMS320C31 Boot Loader 11-411.1.3 TMS320C31 Boot-Loading SequenceThe following is the sequence of events that occur during the boot load of asource pro

Typical Applications1-7Introduction1.2 Typical ApplicationsThe TMS320 family’s versatility, realtime performance, and multiple functionsoffer flexible

TMS320C31 Boot Loader11-5Using the TMS320C31 and TMS320C32 Boot LoadersFigure 11–2.Boot-Loader Memory-Load Flowchartblock loadedaddress of firstBranch

TMS320C31 Boot Loader 11-6Figure 11–3.Boot-Loader Serial-Port Load-Mode FlowchartBegin program executionBlock size –1Transfer data fromserial port tod

TMS320C31 Boot Loader11-7Using the TMS320C31 and TMS320C32 Boot Loaders11.1.4 TMS320C31 Boot Data Stream StructureTable 11–2 shows the data stream str

TMS320C31 Boot Loader 11-8Table 11–2. Source Data Stream Structure Word†Content Valid Data Entries1 Memory width (8, 16, or 32 bits) where source prog

TMS320C31 Boot Loader11-9Using the TMS320C31 and TMS320C32 Boot Loaders11.1.4.1 Examples of External TMS320C31 Memory LoadsTable 11–3, Table 11–4, and

TMS320C31 Boot Loader 11-10Table 11–4. 16-Bit-Wide Configured MemoryAddress Value Comments0x1000 0x10 Memory width = 160x1001 0x00000x1002 0x1058 Memo

TMS320C31 Boot Loader11-11Using the TMS320C31 and TMS320C32 Boot Loaders11.1.4.2 Serial-Port LoadingBoot loads, by way of the ’C31 serial port, are se

TMS320C31 Boot Loader 11-12Table 11–6. TMS320C31 Interrupt and Trap Memory MapsAddress Description809FC1 INT0809FC2 INT1809FC3 INT2809FC4 INT3809FC5 X

TMS320C31 Boot Loader11-13Using the TMS320C31 and TMS320C32 Boot Loaders11.1.6 TMS320C31 Boot-Loader PrecautionsThe boot loader builds a one-word-deep

TMS320C32 Boot Loader 11-1411.2 TMS320C32 Boot LoaderThis section describes how to use the ’C32 microcomputer/boot loader(MCBL/MP) functions.11.2.1 TM

2-1Architectural OverviewThis chapter provides an architectural overview of the ’C3x processor. It includesa discussion of the CPU, memory interface,

TMS320C32 Boot Loader11-15Using the TMS320C31 and TMS320C32 Boot LoadersTable 11–7. Boot-Loader Mode SelectionINT0 INT1 INT2 INT3 Boot Loader Mode Sou

TMS320C32 Boot Loader 11-164) Otherwise, the boot loader attempts a memory boot load. Figure 11–6shows the boot-loader memory flow. If the IF register

TMS320C32 Boot Loader11-17Using the TMS320C31 and TMS320C32 Boot LoadersFigure 11–4.TMS320C32 Boot-Loader Mode-Selection FlowchartNoYesNoYesMCBL/MP =

TMS320C32 Boot Loader 11-18Figure 11–5.Boot-Loader Serial-Port Load FlowchartAccording to the destinationaddress, set correspondingSTRB control regist

TMS320C32 Boot Loader11-19Using the TMS320C31 and TMS320C32 Boot LoadersFigure 11–6.Boot-Loader Memory-Load FlowchartEnd of sourceprogram code(block s

TMS320C32 Boot Loader 11-20Figure 11–7.Handshake Data-Transfer OperationValiddataValiddatai ii iii ivXF1XF0D31-0IACK11.2.4 TMS320C32 Boot Data Stream

TMS320C32 Boot Loader11-21Using the TMS320C31 and TMS320C32 Boot LoadersTable 11–8. Source Data Stream Structure Word†Content Valid Data Entries1 Mem

TMS320C32 Boot Loader 11-22Table 11–8. Source Data Stream Structure (Continued)Valid Data EntriesContentWord†m + 2 Last block destination memory width

TMS320C32 Boot Loader11-23Using the TMS320C31 and TMS320C32 Boot Loaders11.2.5 Boot-Loader Hardware InterfaceThe hardware interface for the memory boo

TMS320C32 Boot Loader 11-24The ’C32 boot loader uses the following peripheral memory-mapped registersas a temporary stack:Timer0 counter register (808

Overview 2-22.1 OverviewThe ’C3x architecture responds to system demands that are based on sophisti-cated arithmetic algorithms that emphasize both ha

12-1PeripheralsThe ’C3x features two timers, a serial port (two serial ports for the ’C30), andan on-chip direct memory access (DMA) controller (2-cha

Timers 12-212.1 TimersThe ’C3x has two 32-bit general-purpose timer modules. Each timer has twosignaling modes and internal or external clocking. You

Timers12-3Peripherals12.1.1 Timer PinsEach timer has one pin associated with the timer clock signal (TCLK) pin. Thispin (TCK) is used as a general-pur

Timers 12-4Figure 12–2. Memory-Mapped Timer LocationsTimer0 global control†Timer0 counter‡Timer0 period‡Timer1 global control†Timer1 counter‡Timer1 pe

Timers12-5PeripheralsTable 12–1. Timer Global-Control Register Bits Summary AbbreviationResetValueName DescriptionFUNC 0 Function Controls the functio

Timers 12-6Table 12–1. Timer Global-Control Register Bits Summary (Continued)Abbreviation DescriptionNameResetValueC/P 0 Clock/pulsemode controlWhen C

Timers12-7Peripherals12.1.4 Timer-Period and Counter RegistersThe 32-bit timer-period register is used to specify the frequency of the timersignaling.

Timers 12-8Figure 12–4. Timer Timing2/f(H1)1/f(H1)1/f(CLKSRC)period register/f(CLKSRC)period register/f(CLKSRC)2 x period register/f(CLKSRC)(a) TSTAT

Timers12-9PeripheralsExample 12–1. Timer Output Generation Examples2H12H1H1(a) INV = 0, C/P = 0 (pulse mode)timer period = 1Also,4H1H1(b) INV = 0, C/P

Timers 12-1012.1.6 Timer Operation ModesThe timer can receive its input and send its output in several different modes,depending upon the setting of C

Overview2-3Architectural OverviewFigure 2–1. TMS320C30 Block DiagramSHZARAU0 ARAU1DISP0, IR0, IR1ALU32-bitbarrelshifterPCRAMblock 1(1K × 32)ROMblock(4

Timers12-11Peripherals12.1.6.2 CLKSRC = 1 and FUNC = 1If CLKSRC = 1 and FUNC = 1 (see Figure 12–6), the timer input comes fromthe internal clock, and

Timers 12-1212.1.6.4 CLKSRC = 0 and FUNC = 1If CLKSRC = 0 and FUNC = 1 (see Figure 12–8), TCLK drives the timer.If INV = 0, all 0-to-1 transitions of

Timers12-13Peripherals12.1.8 Timer InterruptsA timer interrupt is generated whenever the TSTAT bit of the timer control registerchanges from a 0 to a

Timers 12-142) Configure the timer through the timer global-control register (with GO =HLD = 0 ), the timer-counter register, and timer-period registe

Serial Ports12-15Peripherals12.2 Serial PortsThe ’C30 has two totally independent bidirectional serial ports. Both serial portsare identical, and ther

Serial Ports 12-16Figure 12–11. Serial Port Block DiagramReceive Section Transmit SectionReceivetimer (16)Transmittimer (16)Bit counter(8/16/24/32)Bit

Serial Ports12-17PeripheralsFigure 12–12. Memory-Mapped Locations for the Serial PortsSerial-port 0 global controlSerial port 0 FSR/DR/CLKR control§Se

Serial Ports 12-18Figure 12–13. Serial-Port Global-Control Register28RRESETRTINT XINT XTINT31 30 29 27 26 25 24 23 22 21 20 19 18 17 16RLEN XLEN FSRP

Serial Ports12-19PeripheralsTable 12–2. Serial-Port Global-Control Register Bits Summary (Continued)Abbreviation DescriptionNameResetValueHS 0 Handsha

Serial Ports 12-20Table 12–2. Serial-Port Global-Control Register Bits Summary (Continued)Abbreviation DescriptionNameResetValueCLKRP 0 CLKR polarity

Notational Conventionsiv In syntax descriptions, the instruction, command, or directive is in boldtypeface and parameters are in an italic typeface. P

Overview 2-4Figure 2–2. TMS320C31 Block Diagram32-bitbarrelshifterALU4024BootloaderCache(64 × 32)RAMblock 0(1K × 32)RAMblock 1(1K × 32)RDYHOLDHOLDASTR

Serial Ports12-21PeripheralsTable 12–2. Serial-Port Global-Control Register Bits Summary (Continued)Abbreviation DescriptionNameResetValueRINT 0 Recei

Serial Ports 12-2212.2.2 FSX/DX/CLKX Port-Control RegisterThis 32-bit port-control register controls the function of the serial port FSX, DX,and CLKX

Serial Ports12-23PeripheralsTable 12–3. FSX/DX/CLKX Port-Control Register Bits Summary (Continued)Abbreviation DescriptionNameResetValueFSX FUNC 0 FSX

Serial Ports 12-24Table 12–4. FSR/DR/CLKR Port-Control Register Bits Summary AbbreviationResetValueName DescriptionCLKR FUNC 0 Clock receivefunctionCo

Serial Ports12-25Peripherals12.2.4 Receive/Transmit Timer-Control RegisterA 32-bit receive/transmit timer-control register contains the control bits f

Serial Ports 12-26Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)Abbreviation FunctionNameResetValueXCLKSRC 0 Tr

Serial Ports12-27PeripheralsTable 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)Abbreviation FunctionNameResetValueRC

Serial Ports 12-2812.2.6 Receive/Transmit Timer-Period RegisterThe receive/transmit timer-period register is a 32-bit register (see Figure 12–18).Bits

Serial Ports12-29PeripheralsData is shifted to the left (LSB to MSB). Figure 12–20 illustrates what happenswhen words less than 32 bits are shifted in

Serial Ports 12-30Figure 12–21. Serial-Port Clocking in I/O ModeTSTATTimer inXSRTimer inXSRTimer inXSRTimer inXSRTSTATTSTATTSTATDATINDATOUTDATOUT (NC)

Overview2-5Architectural OverviewFigure 2–3. TMS320C32 Block Diagram242440Destination-address registerGlobal-controlregisterTimer0Timer-periodregister

Serial Ports12-31PeripheralsFigure 12–22. Serial-Port Clocking in Serial-Port ModeCLKX FUNC= 1 (serial-port mode)CLKX I/O = 1 (output serial-port CLK)

Serial Ports 12-32The transmit ready (XRDY) signal specifies that the data-transmit register(DXR) is available to be loaded with new data. XRDY goes a

Serial Ports12-33Peripherals12.2.10.1 Continuous Transmit and Receive ModesWhen you choose continuous mode, consecutive writes do not generate orexpec

Serial Ports 12-34When the serial port is placed in the handshake mode, the insertion and deletionof a leading 1 for transmitted data, the sending of

Serial Ports12-35Peripherals12.2.12 Serial-Port Functional OperationThe following paragraphs and figures illustrate the functional timing of thevariou

Serial Ports 12-3612.2.12.1 Fixed Data-Rate Timing OperationFixed data-rate serial-port transfers can occur in two varieties: burst mode andcontinuous

Serial Ports12-37PeripheralsFigure 12–27. Fixed Standard Mode With Back-to-Back Frame SyncA1 AN B1 BN C1DXR loadedwith AXINTDXR loadedwith BXINTRINTXI

Serial Ports 12-38sync inputs are ignored. Additionally, you should set R/XFSM prior to orduring the first word transferred; you must set R/XFSM no la

Serial Ports12-39PeripheralsFigure 12–29. Exiting Fixed Continuous Mode Without Frame Sync, FSX InternalCLKXFSX(internal)DXLOAD DXR SET XFSM RESET XFS

Serial Ports 12-40Variable Standard ModeWhen you transmit continuously in variable data-rate mode with frame sync,timing is the same as for fixed data

Central Processing Unit (CPU) 2-62.2 Central Processing Unit (CPU)The ’C3x devices (’C30, ’C31, and ’C32) have a register-based CPU architec-ture. The

Serial Ports12-41PeripheralsFigure 12–32. Variable Continuous Mode Without Frame SyncCLKX/RFSR/FSX (external)FSX (internal)DX/DRA1 AN B1 BN C1 C2XINTR

Serial Ports 12-4212.2.14.1 Handshake Mode ExampleWhen using the handshake mode, the transmit (FSX/DS/CLKX) and receive(FSR/DR/CLKR) signals transmit

Serial Ports12-43PeripheralsExample 12–4 and Example 12–5 are serial-port register setups for the abovecase. (Assume two ’C3xs have the same system cl

Serial Ports 12-44Example 12–6. CPU Transfer With Serial Port Transmit Polling Method* TITLE: CPU TRANSFER WITH SERIAL-PORT TRANSMIT POLLING METHOD*

Serial Ports12-45Peripherals12.2.14.3 DMA Transfer With Serial Port InterruptExample 12–8 and Example 12–9 of Section 12.3.11 on page 12-74 use theDMA

Serial Ports 12-4612.2.14.5 Serial Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Interface ExampleThe DSP201/2 and DSP101/2 family of D/As and A

Serial Ports12-47Peripherals4) The bit clock drives both the A/D’s and D/A’s XCLK input.5) The ’C3x transmit clock also acts as the input clock on the

DMA Controller 12-4812.3 DMA ControllerThe DMA controller is a programmable peripheral that transfers blocks of datato any location in the memory map

DMA Controller12-49Peripherals12.3.1.1 TMS320C30 and TMS320C31 DMA ControllerThe ’C30 and ’C31 have an on-chip direct memory access (DMA) controllerth

DMA Controller 12-5012.3.2 DMA Basic OperationIf a block of data is to be transferred from one region in memory to another regionin memory (as shown i

Central Processing Unit (CPU)2-7Architectural OverviewFigure 2–4. Central Processing Unit (CPU)MultiplexerMultiplier32-bit barrelshifterExtended-preci

DMA Controller12-51PeripheralsAfter the completion of a block transfer, the DMA controller can be programmedto do several things:Stop until reprogramm

DMA Controller 12-52At reset, each DMA-channel control register is set to 0. This makes the DMAchannels lower-priority than the CPU, sets up the sourc

DMA Controller12-53Peripherals12.3.3.1 DMA Global-Control RegisterThe global-control register controls the state in which the DMA controlleroperates.

DMA Controller 12-54Table 12–6. DMA Global-Control Register Bits SummaryAbbreviationResetValueName DescriptionSTART 00 DMA start control Controls the

DMA Controller12-55PeripheralsTable 12–6. DMA Global-Control Register Bits Summary (Continued)AbbreviationResetValueName DescriptionINCSRC 0 DMA sourc

DMA Controller 12-56Table 12–6. DMA Global-Control Register Bits Summary (Continued)AbbreviationResetValueName DescriptionDMA0 PRI 00 CPU/DMA channel

DMA Controller12-57Peripherals12.3.3.2 Destination-Address and Source-Address RegistersThe DMA destination-address and source-address registers are 24

DMA Controller 12-5812.3.3.3 Transfer-Counter RegisterThe transfer-counter register is a 24-bit register that contains the number ofwords to be transm

DMA Controller12-59PeripheralsFigure 12–40. Transfer-Counter OperationHalt?TC=1IsDMA interrupt generated?TCINT=1Is?to 0CompareDecrementerTransfer-coun

DMA Controller 12-60Figure 12–41. TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable RegisterxxEDINT ETINT1 ETINT0 ERINT1 EXINT131 30 29 28 27 26 25 24

Central Processing Unit (CPU) 2-82.2.1 Floating-Point/Integer MultiplierThe multiplier performs single-cycle multiplications on 24-bit integer and 32-

DMA Controller12-61PeripheralsTable 12–7. CPU/DMA Interrupt-Enable Register Bits AbbreviationResetValueDescriptionEINT0 (CPU) 0 CPU external interrupt

DMA Controller 12-62Table 12–7. CPU/DMA Interrupt-Enable Register Bits (Continued)Abbreviation DescriptionResetValueETINT0 (DMA) 0 DMA timer0 interrup

DMA Controller12-63Peripherals12.3.5.2 Rotating Priority SchemeIn a rotating priority scheme, the last channel serviced becomes the lowestpriority cha

DMA Controller 12-64Table 12–8.TMS320C32 DMA PRI Bits and CPU/DMA Arbitration RulesDMA PRI(Bits 13–12)Description0 0 DMA access is lower priority than

DMA Controller12-65PeripheralsThe DMA and the CPU can respond to the same interrupt if the CPU is notinvolved in any pipeline conflict or in any instr

DMA Controller 12-66Figure 12–44. Mechanism for DMA Source SynchronizationStartDisable DMA interrupts globallyDMA channel performs a readDMA channel p

DMA Controller12-67PeripheralsSource and destination synchronization (SYNC = 1 1)When SYNC = 1 1, the DMA is synchronized to both the source anddestin

DMA Controller 12-68The data transfer rate for a DMA channel (assuming a single-channel accesswith no conflicts between CPU or other DMA channels) is

DMA Controller12-69PeripheralsFigure 12–47. DMA Timing When Destination is On ChipCycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RateSource

DMA Controller12-70Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB BusCycles(H1)1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

CPU Primary Register File2-9Architectural Overview2.3 CPU Primary Register FileThe ’C3x provides 28 registers in a multiport register file that is tig

DMA Controller12-71PeripheralsFigure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued)Cycles(H1)1 2 3 4 5 6 7 8 9 10

DMA Controller12-72Figure 12–49. DMA Timing When Destination is an IOSTRB BusCycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RateSource on ch

DMA Controller12-73Peripherals12.3.9 DMA Initialization/ReconfigurationYou can control the DMA through memory-mapped registers located on thededicated

DMA Controller 12-74The transfer counter has a zero value. However, the transfer counter isdecremented after the DMA read operation finishes (not afte

DMA Controller12-75PeripheralsExample 12–8. Array Initialization With DMA* TITLE: ARRAY INITIALIZATION WITH DMA* .GLOBAL START .DATADMA

DMA Controller 12-76Example 12–9. DMA Transfer With Serial-Port Receive Interrupt* TITLE DMA TRANSFER WITH SERIAL PORT RECEIVE INTERRUPT*.GLOBAL START

DMA Controller12-77PeripheralsExample 12–10 sets up the DMA to transfer data (128 words) from an arraybuffer to the serial port 0 output register with

DMA Controller 12-78Example 12–10. DMA Transfer With Serial-Port Transmit Interrupt (Continued)* DMA INITIALIZATIONLDI @DMA,AR0 ; POINT TO DMA GLOBAL

DMA Controller12-79PeripheralsTransfer a 128-word block of data from on-chip memory to off-chipmemory and generate an interrupt on completion. Invert

13-1Assembly Language InstructionsThe ’C3x assembly language instruction set supports numeric-intensive, signal-processing, and general-purpose applic

CPU Primary Register File 2-10Table 2–1. Primary CPU Registers (Continued)PageSectionAssigned FunctionRegisterNameIR1 Index register 1 3.1.4 3-4BK Blo

Instruction Set 13-213.1 Instruction SetThe ’C3x instruction set is well suited to digital signal processing and othernumeric-intensive applications.

Instruction Set13-3Assembly Language Instructions13.1.2 2-Operand InstructionsThe ’C3x supports 35 2-operand arithmetic and logical instructions. The

Instruction Set 13-413.1.3 3-Operand InstructionsWhereas 2-operand instructions have a single source operand (or shift count)and a destination operand

Instruction Set13-5Assembly Language InstructionsTable 13–4. Program-Control InstructionsInstruction Description Instruction DescriptionBcondBranch co

Instruction Set 13-6Table 13–6. Interlocked-Operations InstructionsInstruction Description Instruction DescriptionLDFI Load floating-point value, inte

Instruction Set13-7Assembly Language InstructionsTable 13–7. Parallel Instructions (Continued)(a) Parallel arithmetic with store instructions (Continu

Instruction Set 13-8Table 13–7. Parallel Instructions (Continued)(b) Parallel load instructionsMnemonic DescriptionLDF|| LDFLoad floating-point valueL

Instruction Set13-9Assembly Language Instructions13.1.8 Illegal InstructionsThe ’C3x has no illegal instruction-detection mechanism. Fetching an illeg

Instruction Set Summary 13-1013.2 Instruction Set SummaryTable 13–8 lists the ’C3x instruction set in alphabetical order. Each table entryprovides the

Instruction Set Summary13-11Assembly Language InstructionsTable 13–8. Instruction Set Summary (Continued)Mnemonic OperationDescriptionBcondBranch cond

CPU Primary Register File2-11Architectural OverviewThe ARAU uses the 32-bit block size register (BK) in circular addressing tospecify the data block s

Instruction Set Summary 13-12Table 13–8. Instruction Set Summary (Continued)Mnemonic OperationDescriptionDBcondDecrement and branch conditionally(stan

Instruction Set Summary13-13Assembly Language InstructionsTable 13–8. Instruction Set Summary (Continued)Mnemonic OperationDescriptionLDIcondLoad inte

Instruction Set Summary 13-14Table 13–8. Instruction Set Summary (Continued)Mnemonic OperationDescriptionNOP No operation Modify ARn if specifiedNORM

Instruction Set Summary13-15Assembly Language InstructionsTable 13–8. Instruction Set Summary (Continued)Mnemonic OperationDescriptionRPTB Repeat bloc

Instruction Set Summary 13-16Table 13–8. Instruction Set Summary (Continued)Mnemonic OperationDescriptionSUBI Subtract integers Dreg – src → DregSUBI3

Parallel Instruction Set Summary13-17Assembly Language Instructions13.3 Parallel Instruction Set SummaryTable 13–9 lists the ’C3x instruction set in a

Parallel Instruction Set Summary 13-18Table 13–9. Parallel Instruction Set Summary (Continued)(a) Parallel arithmetic with store instructions (Continu

Parallel Instruction Set Summary13-19Assembly Language InstructionsTable 13–9. Parallel Instruction Set Summary (Continued)(a) Parallel arithmetic wit

Group Addressing Mode Instruction Encoding 13-2013.4 Group Addressing Mode Instruction EncodingThe six addressing types (covered in Section 6.1, Addre

Group Addressing Mode Instruction Encoding13-21Assembly Language InstructionsFigure 13–1 shows the encoding for the general addressing modes. The nota

Other Registers 2-122.4 Other RegistersThe program-counter (PC) is a 32-bit register containing the address of thenext instruction to fetch. Although

Group Addressing Mode Instruction Encoding 13-22Table 13–10. Indirect Addressing(a) Indirect addressing with displacementMod Field Syntax Operation De

Group Addressing Mode Instruction Encoding13-23Assembly Language InstructionsTable 13–10. Indirect Addressing (Continued)(c) Indirect addressing with

Group Addressing Mode Instruction Encoding 13-2413.4.2 3-Operand Addressing ModesInstructions that use the 3-operand addressing modes, such as ADDI3,

Group Addressing Mode Instruction Encoding13-25Assembly Language InstructionsThe following values of ARn and ARm are valid:ARn,0 ≤ n ≤ 7ARm,0 ≤ m ≤ 7T

Group Addressing Mode Instruction Encoding 13-26address, bits 15–8 the src3 address, and bits 7–0 the src 4 address. Thenotations modn and modm indica

Group Addressing Mode Instruction Encoding13-27Assembly Language Instructions13.4.4 Conditional-Branch Addressing ModesInstructions using the conditio

Condition Codes and Flags 13-2813.5 Condition Codes and FlagsThe ’C3x provides 20 condition codes (00000–10100, excluding 01011) thatyou can place in

Condition Codes and Flags13-29Assembly Language InstructionsFigure 13–6. Status RegisterPRGWstatus(’C32 only)INTconfig(’C32 only)Note: xx = reserved b

Condition Codes and Flags 13-30Table 13–12 lists the condition mnemonic, code, description, and flag for eachof the 20 condition codes.Table 13–12. Co

Condition Codes and Flags13-31Assembly Language InstructionsTable 13–12. Condition Codes and Flags (Continued)(d) Compare to zeroCondition Code Descri

Memory Organization2-13Architectural Overview2.5 Memory OrganizationThe total memory space of the ’C3x is 16M (million) 32-bit words. Program,data, an

Individual Instructions 13-3213.6 Individual InstructionsThis section contains the individual assembly language instructions for the ’C3x.The instruct

Individual Instructions13-33Assembly Language InstructionsTable 13–13. Instruction SymbolsSymbol Meaningsrcsrc1src2src3src4Source operandSource operan

Individual Instructions 13-3413.6.2 Optional Assembler SyntaxThe assembler allows a relaxed syntax form for some instructions. Theseoptional forms sim

Individual Instructions13-35Assembly Language InstructionsEmpty expressions are not allowed for the displacement in indirect mode:LDI *+AR0(),R0is not

Individual Instructions 13-36Use the syntax in Table 13–14 to designate CPU registers in operands.Note the alternate notation Rn, 0 n 27, which is

Individual Instructions13-37Assembly Language Instructions13.6.3 Individual Instruction DescriptionsEach assembly language instruction for the ’C3x is

EXAMPLEExample Instruction13-38 Syntax INST src, dstorINST1 src2, dst1|| INST2 src3, dst2Each instruction begins with an assembler syntax expression.

Example InstructionEXAMPLE13-39 Assembly Language InstructionsOpcodeINST1INST231 24 23 16 8 7 015000srcdstG31 24 23 16 8 7 01511dst1src2dst2src300

EXAMPLEExample Instruction13-40 Example INST @98AEh,R5Before Instruction After InstructionR5 07 6690 0000 R5 00 6690 1000R5 decimal 2.30562500e+02 R5

Absolute Value of Floating PointABSF13-41 Assembly Language InstructionsSyntax ABSF src, dstOperation |src| → dstOperandssrc general addressing mod

Information About Cautions / Related Documentation from Texas Instrumentsv Read This FirstInformation About CautionsThis book contains cautions.This

Memory Organization 2-14Figure 2–5. Memory Organization of the TMS320C30RDYHOLDHOLDASTRBR/WD31–D0A23–A0XRDYMSTRBIOSTRBXR/WXD31–XD0XA12–XA0DMAADDR busD

ABSF||STFParallel ABSF and STF13-42 Syntax ABSFsrc2, dst1|| STFsrc3, dst2Operation |src2| → dst1||src3 → dst2Operandssrc2indirect (disp = 0, 1, IR0, I

Parallel ABSF and STFABSF||STF13-43 Assembly Language InstructionsMode Bit OVM Operation is not affected by OVM bit value.Example ABSF *++AR3(IR1) ,

ABSIAbsolute Value of Integer13-44 Syntax ABSI src, dstOperation |src| → dstOperandssrc general addressing modes (G):0 0 any CPU register0 1 direct1

Absolute Value of IntegerABSI13-45 Assembly Language InstructionsExample 1 ABSI R0,R0orABSI R0Before Instruction After InstructionR0 00 FFFF FFCB R0

ABSI||STIParallel ABSI and STI13-46 Syntax ABSIsrc2, dst1|| STI src3, dst2Operation |src2| → dst1||src3 → dst2Operandssrc2indirect (disp = 0, 1, IR0,

Parallel ABSI and STIABSI||STI13-47 Assembly Language InstructionsStatus Bits These condition flags are modified only if the destination register is

ADDCAdd Integer With Carry13-48 Syntax ADDCsrc, dstOperationdst + src + C → dstOperandssrc general addressing modes (G):0 0 any CPU register0 1 direct

Add Integer With Carry, 3-OperandADDC313-49 Assembly Language InstructionsSyntax ADDC3src2, src1, dstOperationsrc1 + src2 + C → dstOperandssrc1 3-op

ADDC3Add Integer With Carry, 3-Operand13-50 Example 1 ADDC3 *AR5++(IR0),R5,R2 orADDC3 R5,*AR5++(IR0),R2Before Instruction After InstructionR2 00 0000

Add Floating-Point ValuesADDF13-51 Assembly Language InstructionsSyntax ADDFsrc, dstOperationdst + src →dstOperandssrc general addressing modes (G):

Memory Organization2-15Architectural OverviewFigure 2–6. Memory Organization of the TMS320C31RDYHOLDHOLDASTRBR/WD31–D0A23–A0DMAADDR busDMADATA busDADD

ADDFAdd Floating-Point Values13-52 Example ADDF *AR4++(IR1),R5Before Instruction After InstructionR5 05 7980 0000 R5 09 052C 0000AR 4809800 AR4 80992B

Add Floating Point, 3-OperandADDF313-53 Assembly Language InstructionsSyntax ADDF3src2, src1, dstOperationsrc1 + src2 → dstOperandssrc1 3-operand ad

ADDF3Add Floating Point, 3-Operand13-54 Example 1 ADDF3 R6,R5,R1orADDF3 R5,R6,R1Before Instruction After InstructionR1 00 0000 0000 R1 09 052C 0000R5

Parallel ADDF3 and STFADDF3||STF13-55 Assembly Language InstructionsSyntax ADDF3src2, src1, dst1|| STF src3, dst2Operationsrc1 + src2 → dst1||src3 →

ADDF3||STFParallel ADDF3 and STF13-56 OVM Operation is not affected by OVM bit value.Example ADDF3 *+AR3(IR1),R2,R5|| STF R4,*AR2Before Instruction Af

Add IntegerADDI13-57 Assembly Language InstructionsSyntax ADDI src, dstOperationdst + src → dstOperandssrc general addressing modes (G):0 0 any CPU

ADDI3Add Integer, 3-Operand13-58 Syntax ADDI3<src2 >,<src1 >,<dst >Operationsrc1 + src2 → dstOperandssrc1 3-operand addressing modes

Add Integer, 3-OperandADDl313-59 Assembly Language InstructionsExample 1 ADDI3 R4,R7,R5Before Instruction After InstructionR4 00 0000 00DC R4 00 000

ADDI3||STIParallel ADDI3 and STI13-60 Syntax ADDI3 src2, src1, dst1|| STI src3, dst2Operationsrc1 + src2 → dst1||src3 → dst2Operandssrc1register (Rn1,

Parallel ADDl3 and STIADDl3||STI13-61 Assembly Language InstructionsOVM Operation is affected by OVM bit value.Example ADDI3 *AR0––(IR0),R5,R0 STI

STRB0_B3/A-1HOLDHOLDAPRGWR/WD31–D0A23–A0DMAADDR busDMADATA busDADDR2 busDADDR1 busDDATA busPADDR busPDATA busProgram counter/instruction registerCPUDM

ANDBitwise-Logical AND13-62 Syntax AND src, dstOperandsdst AND src → dstOperandssrc general addressing modes (G):0 0 any CPU register0 1 direct1 0 in

Bitwise-Logical AND, 3-OperandAND313-63 Assembly Language InstructionsSyntax AND3 src2, src1, dstOperationsrc1 AND src2 → dstOperandssrc1 3-operand

AND3Bitwise-Logical AND, 3-Operand13-64 Example 1 AND3 *AR0––(IR0),*+AR1,R4Before Instruction After InstructionR4 00 0000 0000 R4 00 0000 0020AR0 80 9

Parallel AND3 and STIAND3||STI13-65 Assembly Language InstructionsSyntax AND3 src2, src1, dst1 STI src3, dst2Operationsrc1 AND src2 → dst1||src3

AND3||STIParallel AND3 and STI13-66 OVM Operation is not affected by OVM bit value.Example AND3 *+AR1(IR0),R4,R7|| STI R3,*AR2Before Instruction Af

Bitwise-Logical AND With ComplementANDN13-67 Assembly Language InstructionsSyntax ANDN src, dstOperationdst AND ∼src → dstOperandssrc general addre

ANDNBitwise-Logical AND With Complement13-68 Example ANDN @980Ch,R2Before Instruction After InstructionR2 00 0000 0C2F R2 00 0000 042DDP 080 DP 080LUF

Bitwise-Logical ANDN, 3-OperandANDN313-69 Assembly Language InstructionsSyntax ANDN3 src2, src1, dstOperationsrc1 AND ∼src2 → dstOperandssrc1 3-ope

ANDN3Bitwise-Logical ANDN, 3-Operand13-70 Example 1 ANDN3 R5,R3,R7Before Instruction After InstructionR3 00 0000 0C2F R3 00 0000 0C2FR5 00 0000 0A02 R

Arithmetic ShiftASH13-71 Assembly Language InstructionsSyntax ASH count, dstOperation If (count ≥ 0):dst << count →dstElse:dst >> |coun

Memory Organization2-17Architectural Overview2.5.2 Memory Addressing ModesThe ’C3x supports a base set of general-purpose instructions as well as arit

ASHArithmetic Shift13-72 Status Bits These condition flags are modified only if the destination register is R7–R0.LUF UnaffectedLV 1 if an integer ove

Arithmetic Shift, 3-OperandASH313-73 Assembly Language InstructionsSyntax ASH3 count, src, dstOperation If (count ≥ 0):src << count → dstElse

ASH3Arithmetic Shift, 3-Operand13-74 Status Bits These condition flags are modified only if the destination register is R7–R0.LUF UnaffectedLV 1 if an

Arithmetic Shift, 3-OperandASH313-75 Assembly Language InstructionsExample 2 ASH3 R1,R3,R5Before Instruction After InstructionR1 00 FFFF FFF8 R1 00

ASH3||STIParallel ASH3 and STI13-76 Syntax ASH3count, src2, dst1|| STI src3, dst2Operation If (count ≥ 0):src2 << count → dst1Else:src2 >>

Parallel ASH3 and STIASH3||STI13-77 Assembly Language InstructionsArithmetic right shift:sign of src2 → src2 → CIf the count operand is 0, no shift

ASH3||STIParallel ASH3 and STI13-78 Example ASH3 R1,*AR6++(IR1),R0|| STI R5,*AR2Before Instruction After InstructionR0 00 0000 0000 R0 00 FFFF FFAER1

Branch Conditionally (Standard)Bcond13-79 Assembly Language InstructionsSyntax Bcond srcOperation If cond is true:If src is in register-addressing

BcondBranch Conditionally (Standard)13-80 Example BZ R0Before Instruction After InstructionR0 00 0003 FF00 R0 00 0003 FF00PC 2B00 PC 3 FF00LUF 0 LUF

Branch Conditionally (Delayed)BcondD13-81 Assembly Language InstructionsSyntax BcondD srcOperation If cond is true:If src is in register-addressing

Internal Bus Operation 2-182.6 Internal Bus OperationMuch of the ’C3x’s high performance is due to internal busing and parallelism.Separate buses allo

BcondDBranch Conditionally (Delayed)13-82 Example BNZD 36 (36 = 24h)Before Instruction After InstructionPC 0050 PC 0077LUF 0 LUF 0LV 0 LV 0UF 0 UF 0N

Branch Unconditionally (Standard)BR13-83 Assembly Language InstructionsSyntax BR srcOperationsrc → PCOperandssrc long-immediate addressing modeOpco

BRDBranch Unconditionally (Delayed)13-84 Syntax BRD srcOperationsrc → PCOperandssrc long-immediate addressing modeOpcode31 24 23 16 8 7 01501100 100s

Call SubroutineCALL13-85 Assembly Language InstructionsSyntax CALL srcOperation Next PC → *++SPsrc → PCOperandssrc long-immediate addressing modeOp

CALLcondCall Subroutine Conditionally13-86 Syntax CALLcond srcOperation If cond is true:Next PC → *++SPIf src is in register addressing mode (Rn, 0 ≤

Call Subroutine ConditionallyCALLcond13-87 Assembly Language InstructionsExample CALLNZ R5Before Instruction After InstructionR5 00 0000 0789 R5 00

CMPFCompare Floating-Point Value13-88 Syntax CMPF src, dstOperationdst – srcOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 7)0 1

Compare Floating-Point ValueCMPF13-89 Assembly Language InstructionsExample CMPF *+AR4,R6Before Instruction After InstructionR6 07 0C80 0000 R6 07 0

CMPF3Compare Floating-Point Value, 3-Operand13-90 Syntax CMPF3 src2, src1Operationsrc1 – src2Operandssrc1 3-operand addressing modes (T):0 0 register

Compare Floating-Point Value, 3-OperandCMPF313-91 Assembly Language InstructionsExample CMPF3 *AR2,*AR3––(1)Before Instruction After InstructionAR2

External Memory Interface2-19Architectural Overview2.7 External Memory InterfaceThe ’C30 provides two external interfaces: the primary bus and the exp

CMPICompare Integer13-92 Syntax CMPI src, dstOperationdst – srcOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 27)0 1 direct1 0 in

Compare Integer, 3-OperandCMPI313-93 Assembly Language InstructionsSyntax CMPI3 src2, src1Operationsrc1 – src2Operandssrc1 3-operand addressing mod

CMPI3Compare Integer, 3-Operand13-94 Example CMPI3 R7,R4Before Instruction After InstructionR4 00 0000 0898 R4 00 0000 0898R7 00 0000 03E8 R7 00 0000

Decrement and Branch Conditionally (Standard)DBcond13-95 Assembly Language InstructionsSyntax DBcond ARn, srcOperation ARn – 1 → ARnIf cond is true

DBcondDecrement and Branch Conditionally (Standard)13-96 Cycles 4Status Bits LUF UnaffectedLV UnaffectedUF UnaffectedN UnaffectedZ UnaffectedV Unaffec

Decrement and Branch Conditionally (Delayed)DBcondD13-97 Assembly Language InstructionsSyntax DBcondD ARn, srcOperation ARn – 1 → ARnIf cond is tru

DBcondDDecrement and Branch Conditionally (Delayed)13-98 Cycles 1Status Bits LUF UnaffectedLV UnaffectedUF UnaffectedN UnaffectedZ UnaffectedV Unaffec

Floating-Point-to-Integer ConversionFIX13-99 Assembly Language InstructionsSyntax FIX src, dstOperation fix(src) → dstOperandssrc general addressin

FIXFloating-Point-to-Integer Conversion13-100 Example FIX R1,R2Before Instruction After InstructionR1 0A 2820 0000 R1 0A 2820 0000R2 00 0000 0000 R2

Parallel FIX and STIFIX||STI13-101 Assembly Language InstructionsSyntax FIX src2, dst1|| STI src3, dst2Operation fix(src2) → dst1||src3 → dst2Ope

External Memory Interface 2-202.7.2 TMS320C32 8-, 16-, and 32-Bit Data MemoryThe ’C32 external memory interface can load and store 8-, 16-, or 32-bit

FIX||STIParallell FIX and STI13-102 Status Bits These condition flags are modified only if the destination register is R7–R0.LUF UnaffectedLV 1 if an

Integer-to-Floating-Point ConversionFLOAT13-103 Assembly Language InstructionsSyntax FLOAT src, dstOperation float (src) → dstOperandssrc general a

FLOATInteger-to-Floating-Point Conversion13-104 Example FLOAT *++AR2(2),R5Before Instruction After InstructionR5 00 034C 2000 R5 00 72E0 0000AR2 80 98

Parallel FLOAT and STFFLOAT||STF13-105 Assembly Language InstructionsSyntax FLOATsrc2, dst1|| STF src3, dst2Operation float(src2 ) → dst1||src3 → ds

FLOAT||STFParallel FLOAT and STF13-106 Example FLOAT *+AR2(IR0),R6|| STF R7,*AR1Before Instruction After InstructionR6 00 0000 0000 R6 07 2E00 0000R7

Interrupt AcknowledgeIACK13-107 Assembly Language InstructionsSyntax IACK srcOperation Perform a dummy read operation with IACK = 0.At end of dummy

IACKInterrupt Acknowledge13-108 Example IACK *AR5Before Instruction After InstructionIACK1 IACK 1PC 300 PC 301LUF 0 LUF 0LV 0 LV 0UF 0 UF 0N 0 N 0Z 0

Idle Until InterruptIDLE13-109 Assembly Language InstructionsSyntax IDLEOperation 1 → ST(GIE)Next PC → PCIdle until interrupt.Operands NoneOpcode31

IDLE2Low-Power Idle13-110 Syntax IDLE2 (supported by: ’LC31, ’C32, ’C30 silicon revision 7.x orgreater, ’C31 silicon revision 5.x or greater)Operatio

Low-Power IdleIDLE213-111 Assembly Language InstructionsFor correct device operation, the three instructions after a delayedbranch should not be IDL

Interrupts2-21Architectural Overview2.8 InterruptsThe ’C3x supports four external interrupts (INT3–INT0), a number of internalinterrupts, and a nonmas

LDELoad Floating-Point Exponent13-112 Syntax LDE src, dstOperationsrc(exp) → dst(exp)Operandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n

Load Floating-Point ExponentLDE13-113 Assembly Language InstructionsExample LDE R0,R5Before Instruction After InstructionR0 02 0005 6F30 R0 02 0005

LDFLoad Floating-Point Value13-114 Syntax LDF src, dstOperationsrc → dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 7)0 1 dire

Load Floating-Point Value ConditionallyLDFcond13-115 Assembly Language InstructionsSyntax LDFcond src, dstOperation If cond is true:src → dst.Else:

LDFcondLoad Floating-Point Value Conditionally13-116 Example LDFZ R3,R5Before Instruction After InstructionR3 2C FF2C D500 R3 2C FF2C D500 R5 5F 0000

Load Floating-Point Value, InterlockedLDFI13-117 Assembly Language InstructionsSyntax LDFI src, dstOperation Signal interlocked operationsrc → dstO

LDFILoad Floating-Point Value, Interlocked13-118 Example LDFI *+AR2,R7Before Instruction After InstructionR7 00 0000 0000 R7 05 84C0 0000AR2 80 98F1 A

Parallel LDF and LDFLDF||LDF13-119 Assembly Language InstructionsSyntax LDF src2, dst2|| LDF src1, dst1Operationsrc2 → dst2||src1 → dst1Operandssr

LDF||LDFParallel LDF and LDF13-120 Example LDF *––AR1(IR0),R7|| LDF *AR7++(1),R3Before Instruction After InstructionR3 00 0000 0000 R0 00 0000 0008R7

Parallel LDF and STFLDF||STF13-121 Assembly Language InstructionsSyntax LDF src2, dst1|| STF src3, dst2Operationsrc2 → dst1||src3 → dst2Operandssrc2

Peripherals 2-222.9 PeripheralsAll ’C3x peripherals are controlled through memory-mapped registers on a dedi-cated peripheral bus. This peripheral bus

LDF||STFParallel LDF and STF13-122 Example LDF *AR2––(1),R1|| STF R3,*AR4++(IR1)Before Instruction After InstructionR1 00 0000 0000 R1 07 0C80 0000R3

Load IntegerLDI13-123 Assembly Language InstructionsSyntax LDI src, dstOperationsrc → dstOperandssrc general addressing modes (G):0 0 any CPU regis

LDILoad Integer13-124 Example LDI *–AR1(IR0),R5Before Instruction After InstructionR5 00 0000 03C5 R5 00 0000 0026AR1 2C AR1 2CIR0 5 IR0 5LUF 0 LUF 0L

Load Integer ConditionallyLDIcond13-125 Assembly Language InstructionsSyntax LDIcond src, dstOperation If cond is true:src → dst,Else:dst is unchan

LDIcondLoad Integer Conditionally13-126 Example LDIZ *ARO++,R6Before Instruction After InstructionR6 00 0000 0FE2 R6 00 0000 0FE2AR0 80 98F0 AR0 80 98

Load Integer, InterlockedLDII13-127 Assembly Language InstructionsSyntax LDII src, dstOperation Signal interlocked operationsrc → dstOperandssrc ge

LDIILoad Integer, Interlocked13-128 Example LDII @985Fh,R3Before Instruction After InstructionR3 00 0000 0000 R3 00 0000 00DCDP 80 DP 80LUF 0 LUF 0LV

Parallel LDI and LDILDI||LDI13-129 Assembly Language InstructionsSyntax LDI src2, dst2|| LDI src1, dst1Operationsrc2 → dst2||src1 → dst1Operandssr

LDI||LDIParallel LDI and LDI13-130 Example LDI *–AR1(1),R7|| LDI *AR7++(IR0),R1Before Instruction After InstructionR1 00 0000 0000 R1 00 0000 02EER7 0

Parallel LDI and STILDI||STI13-131 Assembly Language InstructionsSyntax LDI src2, dst1|| STI src3, dst2Operationsrc2 → dst1||src3 → dst2Operandssr

Peripherals2-23Architectural Overview2.9.1 TimersThe two timer modules are general-purpose 32-bit timer/event counters withtwo signaling modes and int

LDI||STIParallel LDI and STI13-132 Example LDI *–AR1(1),R2|| STI R7,*AR5++(IR0)Before Instruction After InstructionR2 00 0000 0000 R2 00 0000 00DCR7 0

Load Floating-Point MantissaLDM13-133 Assembly Language InstructionsSyntax LDM src, dstOperationsrc(man) →dst(man)Operandssrc general addressing mo

LDPLoad Data-Page Pointer13-134 Syntax LDP src, DPOperationsrc→ data-page pointerOperandssrc is the 8 MSBs of the absolute 24-bit source address (src

Divide Clock by 16LOPOWER13-135 Assembly Language InstructionsSyntax LOPOWER (supported by: ’LC31 and ’C32, ’C31 silicon revision 5.0 or greater, ’C

LSHLogical Shift13-136 Syntax LSH count, dstOperation If count ≥ 0:dst << count → dstElse:dst >> |count| → dstOperandscount general addre

Logical ShiftLSH13-137 Assembly Language InstructionsCycles 1Status Bits These condition flags are modified only if the destination register is R7–R

LSH3Logical Shift, 3-Operand13-138 Syntax LSH3 count, src, dstOperation If count ≥ 0:src << count → dstElse:src >> |count| → dstOperands

Logical Shift, 3-OperandLSH313-139 Assembly Language InstructionsCycles 1Status Bits These condition flags are modified only if the destination regi

LSH3Logical Shift, 3-Operand13-140 Example 2 LSH3 *–AR4(IR1),R5,R3Before Instruction After InstructionR3 00 0000 0000 R3 00 0001 2C00R5 00 12C0 0000 R

Parallel LSH3 and STILSH3||STI13-141 Assembly Language InstructionsSyntax LSH3 count, src2, dst1|| STI src3, dst2Operation If count ≥ 0:src2 <<

Related Documentation from Texas Instruments / Referencesvi TMS320C3x C Source Debugger User’s Guide (literature numberSPRU053) tells you how to invok

Direct Memory Access (DMA) 2-242.10 Direct Memory Access (DMA)The on-chip DMA controller can read from or write to any location in thememory map witho

LSH3||STIParallel LSH3 and STI13-142 Logical right shift:0 → src2 → CIf the count operand is 0, no shift is performed, and the carry bit is set to 0.T

Parallel LSH3 and STILSH3||STI13-143 Assembly Language InstructionsExample 1 LSH3 R2,*++AR3(1),R0|| STI R4,*–AR5Before Instruction After Instruction

LSH3||STIParallel LSH3 and STI13-144 Example 2 LSH3 R7,*AR2––(1),R2|| STI R0,*+AR0(1)Before Instruction After InstructionR0 00 0000 012C R0 00 0000 01

Restore Clock to Regular SpeedMAXSPEED13-145 Assembly Language InstructionsSyntax MAXSPEED (supported by ’C31, ’C32, ’C31 silicon revision 5.0 or gr

MPYFMultiply Floating-Point Value13-146 Syntax MPYF src, dstOperationdst × src → dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n

Multiply Floating-Point Value, 3-OperandMPYF313-147 Assembly Language InstructionsSyntax MPYF3 src2, src1, dstOperationsrc1 × src2 → dstOperandssrc

MPYF3Multiply Floating-Point Value, 3-Operand13-148 Example 1 MPYF3 R0,R7,R1Before Instruction After InstructionR0 05 7B40 0000 R0 05 7B40 0000R1 00 0

Parallel MPYF3 and ADDF3MPYF3||ADDF313-149 Assembly Language InstructionsSyntax MPYF3 srcA, srcB, dst1 || ADDF3 srcC, srcD, dst2OperationsrcA × sr

MPYF3||ADDF3Parallel MPYF3 and ADDF313-150 This instruction’s operands have been augmented in the following devices:’C31 silicon version 6.0 or greate

Parallel MPYF3 and ADDF3MPYF3||ADDF313-151 Assembly Language Instructions10src1×src2, src3 + src411src3×src1, src2 + src4Opcode31 24 23 16 8 7 01510

Direct Memory Access (DMA)2-25Architectural OverviewFigure 2–10. DMA ControllerDMAADDR busDMADATA busDMA controllerGlobal-control registerSource-addre

MPYF3||ADDF3Parallel MPYF3 and ADDF313-152 Example MPYF3 *AR5++(1),*––AR1(IR0),R0|| ADDF3 R5,R7,R3Note: Cycle CountOne cycle if:src3 and src4 are in i

Parallel MPYF3 and STFMPYF3||STF13-153 Assembly Language InstructionsSyntax MPYF3src2, src1, dst || STF src3, dst2Operationsrc1 × src2 → dst1||src3

MPYF3||STFParallel MPYF3 and STF13-154 Status Bits These condition flags are modified only if the destination register is R7–R0.LUF 1 if a floating-po

Parallel MPYF3 and SUBF3MPYF3||SUBF313-155 Assembly Language InstructionsSyntax MPYF3srcA, srcB, dst1 || SUBF3srcC, srcD, dst2OperationsrcA × srcB

MPYF3||ADDF3Parallel MPYF3 and ADDF313-156 This instruction’s operands have been augmented in the following devices:’C31 silicon version 6.0 or greate

Parallel MPYF3 and SUBF3MPYF3||SUBF313-157 Assembly Language InstructionsOpcode31 24 23 16 8 7 01510 0001src4src3Psrc1src2d1 d2Description A floatin

MPYF3||SUBF3Parallel MPYF3 and SUBF313-158 Status Bits These condition flags are modified only if the destination register is R7–R0.LUF 1 if a floatin

Multiply IntegerMPYI13-159 Assembly Language InstructionsSyntax MPYI src, dstOperationdst ×src →dstOperandssrc general addressing modes (G):0 0 any

MPYIMultiply Integer13-160 Example MPYI R1,R5Before Instruction After InstructionR1 00 0033 C251 R1 00 0033 C251R5 00 0078 B600 R5 00 E21D 9600LUF 0 L

Multiply Integer, 3-OperandMPYI313-161 Assembly Language InstructionsSyntax MPYI3 src2, src1, dstOperationsrc1 × src2 → dstOperandssrc1 3-operand ad

TMS320C30, TMS320C31, and TMS320C32 Differences 2-262.11 TMS320C30, TMS320C31, and TMS320C32 DifferencesTable 2–2 shows the major differences between

MPYI3Multiply Integer, 3-Operand13-162 Example 1 MPYI3 *AR4,*–AR1(1),R2Before Instruction After InstructionR2 00 0000 0000 R2 00 0000 94ACAR1 80 98F3

Parallel MPYI3 and ADDI3MPYI3||ADDI313-163 Assembly Language InstructionsSyntax MPYI3 srcA, srcB, dst1 || ADDI3 srcC, srcD, dst2OperationsrcA × src

MPYI3||ADDI3Parallel MPYI3 and ADDI313-164 This instruction’s operands have been augmented in the following devices:’C31 silicon version 6.0 or greate

Parallel MPYI3 and ADDI3MPYI3||ADDI313-165 Assembly Language InstructionsOpcode31 2423 16 8 7 01510 001 0 Psrc4src3src1src2d1 d2Description An integ

MPYl3||ADDl3Parallel MPYl3 and ADD1313-166 Before Instruction After InstructionR0 00 0000 0000 R0 00 0000 07D0R3 00 0000 0000 R3 00 0000 0000R4 00 000

Parallel MPYI3 and STIMPYI3||STI13-167 Assembly Language InstructionsSyntax MPYI3src2, src1, dst1|| STI src3, dst2Operationsrc1 × src2 → dst1||src3

MPYI3||STIParallel MPYl3 and STI13-168 Status Bits These condition flags are modified only if the destination register is R7–R0.LUF UnaffectedLV 1 if

Parallel MPYI3 and SUBI3MPYI3||SUBI313-169 Assembly Language InstructionsSyntax MPYI3 srcA, srcB, dst1|| SUBI3 srcC, srcD, dst2OperationsrcA × src

MPYI3||SUBI3Parallel MPYI3 and SUBI313-170 This instruction’s operands have been augmented in the following devices:’C31 silicon version 6.0 or greate

Parallel MPYI3 and SUBI3MPYI3||SUBI313-171 Assembly Language InstructionsVersion 5.0 or laterPsrcA srcB srcD srcC00src3×src4, src1 + src201src3×src1

TMS320C30, TMS320C31, and TMS320C32 Differences2-27Architectural OverviewTable 2–2. Feature Set ComparisonFeature ’C30 ’C31 ’C32External bus Two buses

MPYI3||SUBI3Parallel MPYI3 and SUBI313-172 orMPYI3 *++AR0(1),R2,R0|| SUBI3 *AR5––(IR1),R4,R2Before Instruction After InstructionR0 00 0000 0000 R0 00

Negative Integer With BorrowNEGB13-173 Assembly Language InstructionsSyntax NEGB src, dstOperation 0 – src – C → dstOperandssrc general addressing m

NEGFNegate Floating-Point Value13-174 Syntax NEGF src, dstOperation 0 – src → dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 7

Negate Floating-Point ValueNEGF13-175 Assembly Language InstructionsExample NEGF *++AR3(2),R1Before Instruction After InstructionR1 05 7B40 0025 R1

NEGF||STFParallel NEGF and STF13-176 Syntax NEGFsrc2, dst1|| STF src3, dst2Operation 0 – src2 → dst1||src3 → dst2Operandssrc2indirect (disp = 0, 1, IR

Parallel NEGF and STFNEGF||STF13-177 Assembly Language InstructionsExample NEGF *AR4––(1),R7|| STF R2,*++AR5(1)Before Instruction After InstructionR

NEGINegate Integer13-178 Syntax NEGI src, dstOperation 0 – src → dstOperandssrc general addressing modes (G):0 0 any CPU register0 1 direct1 0 indirec

Parallel NEGI and STINEGI||STI13-179 Assembly Language InstructionsSyntax NEGI src2, dst1|| STI src3, dst2Operation 0 – src2 → dst1|| src3 → dst2Ope

NEGI||STIParallel NEGI and STI13-180 Example NEGI *–AR3,R2|| STI R2,*AR1++Before Instruction After InstructionR2 00 0000 0019 R2 00 FFFF FF24AR1 80 98

No OperationNOP13-181 Assembly Language InstructionsSyntax NOP srcOperation No ALU or multiplier operations.ARn is modified if src is specified in

3-1CPU RegistersThe central processing unit (CPU) register file contains 28 registers that canbe operated on by the multiplier and arithmetic logic un

NORMNormalize13-182 Syntax NORM src, dstOperation norm (src) → dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 7)0 1 direct1 0

NormalizeNORM13-183 Assembly Language InstructionsExample NORM R1,R2Before Instruction After InstructionR1 04 0000 3AF5 R1 04 0000 3AF5R2 07 0C80 00

NOTBitwise-Logical Complement13-184 Syntax NOT src, dstOperation ∼src → dstOperandssrc general addressing modes (G):0 0 any CPU register0 1 direct1 0

Bitwise-Logical ComplementNOT13-185 Assembly Language InstructionsExample NOT @982Ch,R4Before Instruction After InstructionR4 00 0000 0000 R4 00 FFF

NOT||STIParallel NOT and STI13-186 Syntax NOT src2, dst1 || STI src3, dst2Operation ∼src2 → dst1||src3 → dst2Operandssrc2indirect (disp = 0, 1, IR0, I

Parallel NOT and STINOT||STI13-187 Assembly Language InstructionsExample NOT *+AR2,R3|| STI R7,*––AR4 (IR1)Before Instruction After InstructionR3 00

ORBitwise-Logical OR13-188 Syntax OR src, dstOperationdst OR src → dstOperandssrc general addressing modes (G):0 0 any CPU register0 1 direct1 0 indi

Bitwise-Logical OROR13-189 Assembly Language InstructionsExample OR *++AR1(IR1),R2Before Instruction After InstructionR2 00 1256 0000 R2 00 1256 2BC

OR3Bitwise-Logical OR, 3-Operand13-190 Syntax OR3 src2, src1, dstOperationsrc1 OR src2 → dstOperandssrc1 3-operand addressing modes (T):0 0 register

Bitwise-Logical OR, 3-OperandOR313-191 Assembly Language InstructionsExample OR3 *++AR1(IR1),R2,R7Before Instruction After InstructionR2 00 1256 000

CPU Multiport Register File 3-23.1 CPU Multiport Register FileThe ’C3x provides 28 registers in a multiport register file that is tightly coupled toth

OR3||STIParallel OR3 and STI13-192 Syntax OR3 src2, src1, dst1 || STI src3, dst2Operationsrc1 OR src2 → dst1|src3 → dst2Operandssrc1 register (Rn1, 0

Parallel OR3 and STIOR3||STI13-193 Assembly Language InstructionsStatus Bits These condition flags are modified only if the destination register is

POPPop Integer13-194 Syntax POP dstOperation *SP–– → dstOperandsdst register (Rn, 0 ≤ n ≤ 27)Opcode31 24 23 16 8 7 015000 01 01 01dst10 000 000 00 0

Pop Floating-Point ValuePOPF13-195 Assembly Language InstructionsSyntax POPF dstOperation *SP–– → dst1Operandsdst register (Rn, 0 ≤ n ≤ 7)Opcode31

PUSHPUSH Integer13-196 Syntax PUSH srcOperationsrc → *++SPOperandssrc register (Rn, 0 ≤ n ≤ 27)Opcode31 24 23 16 8 7 015000 01 11 01src00100000000000

PUSH Floating-Point ValuePUSHF13-197 Assembly Language InstructionsSyntax PUSHF srcOperationsrc → *++SPOperandssrc register (Rn, 0 ≤ n ≤ 7)Opcode31

RETIcondReturn From Interrupt Conditionally13-198 Syntax RETIcondOperation If cond is true:*SP – – → PC1 → ST (GIE).Else, continue.Operands NoneOpcode

Return From Interrupt ConditionallyRETIcond13-199 Assembly Language InstructionsExample RETINZBefore Instruction After InstructionPC 0456 PC 0123SP

RETScondReturn From Subroutine Conditionally13-200 Syntax RETScondOperation If cond is true:*SP– – → PC.Else, continue.Operands NoneOpcode31 2423 16 8

Return From Subroutine ConditionallyRETScond13-201 Assembly Language InstructionsExample RETSGEBefore Instruction After InstructionPC 0123 PC 0456SP

CPU Multiport Register File3-3CPU RegistersThe registers also have some special functions for which they are particularlyappropriate. For example, the

RNDRound Floating-Point Value13-202 Syntax RND src, dstOperation rnd(src) → dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 7)0

Round Floating-Point ValueRND13-203 Assembly Language InstructionsExample RND R5,R2Before Instruction After InstructionR2 00 0000 0000 R2 07 33C1 6F

ROLRotate Left13-204 Syntax ROL dstOperationdst left-rotated 1 bit → dstOperandsdst register (Rn, 0 ≤ n ≤ 27)Opcode31 24 23 16 8 7 015000 1 0 10 10ds

Rotate Left Through CarryROLC13-205 Assembly Language InstructionsSyntax ROLC dstOperationdst left-rotated one bit through carry bit → dstOperandsd

ROLCRotate Left Through Carry13-206 Example 2 ROLC R3Before Instruction After InstructionR3 00 8000 4281 R3 00 0000 8502LUF 0 LUF 0LV 0 LV 0UF 0 UF 0N

Rotate RightROR13-207 Assembly Language InstructionsSyntax ROR dstOperationdst right-rotated one bit through carry bit → dstOperandsdst register (R

RORCRotate Right Through Carry13-208 Syntax RORC dstOperationdst right-rotated one bit through carry bit → dstOperandsdst register (Rn, 0 ≤ n ≤ 27)Op

Repeat BlockRPTB13-209 Assembly Language InstructionsSyntax RPTB srcOperationsrc → RE1 → ST (RM)Next PC → RSOperandssrc long-immediate addressing m

RPTBRepeat Block13-210 Example RPTB 127hBefore Instruction After InstructionPC 0123 PC 0124RE 0 RE 127RS 0 RS 124ST 0 ST 100LUF 0 LUF 0LV 0 LV 0UF 0

Repeat Single InstructionRPTS13-211 Assembly Language InstructionsSyntax RPTS srcOperationsrc → RC1 → ST (RM)1 → SNext PC → RSNext PC → REOperandss

CPU Multiport Register File 3-43.1.2 Auxiliary Registers (AR7–AR0)The CPU can access the eight 32-bit auxiliary registers (AR7–AR0), and thetwo auxili

RPTSRepeat Single Instruction13-212 Example RPTS AR5Before Instruction After InstructionAR5 00 00FF AR5 00 00FFPC 0123 PC 0124RC 0 RC 0FFRE 0 RE 124RS

Signal, InterlockedSIGI13-213 Assembly Language InstructionsSyntax SIGIOperation Signal interlocked operation.Wait for interlock acknowledge.Clear i

STFStore Floating-Point Value13-214 Syntax STF src, dstOperationsrc → dstOperandssrc register (Rn, 0 ≤ n ≤ 7)dst general addressing modes (G):0 1 dir

Store Floating-Point Value, InterlockedSTFI13-215 Assembly Language InstructionsSyntax STFI src, dstOperationsrc → dstSignal end of interlocked ope

STFIStore Floating-Point Value, Interlocked13-216 Note:The STFI instruction is not interruptible because it completes when ready issignaled. See Secti

Parallel Store Floating-Point ValueSTF||STF13-217 Assembly Language InstructionsSyntax STF src2, dst2|| STF src1, dst1Operationsrc2 → dst2||src1 → d

STF||STFParallel Store Floating-Point Value13-218 Example STF R4,*AR3––|| STF R3,*++AR5Before Instruction After InstructionR3 07 33C0 0000 R3 07 33C0

Store IntegerSTI13-219 Assembly Language InstructionsSyntax STI src, dstOperationsrc → dstOperandssrc register (Rn, 0 ≤ n ≤ 27)dst general addressi

STIIStore Integer, Interlocked13-220 Syntax STII src, dstOperationsrc → dstSignal end of interlocked operationOperandssrc register (Rn, 0 ≤ n ≤ 27)ds

Parallel STI and STISTI||STI13-221 Assembly Language InstructionsSyntax STIsrc2, dst2|| STIsrc1, dst1Operationsrc2 → dst2||src1 →dst1Operandssrc1reg

CPU Multiport Register File3-5CPU Registers3.1.7 Status (ST) Register The status (ST) register contains global information about the state of the CPU.

STI||STIParallel STI and STI13-222 Example STI R0,*++AR2(IR0)|| STI R5,*AR0Before Instruction After InstructionR0 00 0000 00DC R0 00 0000 00DCR5 00 00

Subtract Integer With BorrowSUBB13-223 Assembly Language InstructionsSyntax SUBB src, dstOperationdst – src – C → dstOperandssrc general addressin

SUBB3Subtract Integer With Borrow, 3-Operand13-224 Syntax SUBB3 src2, src1, dstOperationsrc1 – src2 – C → dstOperandssrc1 3-operand addressing modes

Subtract Integer With Borrow, 3-OperandSUBB313-225 Assembly Language InstructionsExample SUBB3 R5,*AR5++(IR0),R0Before Instruction After Instruction

SUBCSubtract Integer Conditionally13-226 Syntax SUBC src, dstOperation If (dst – src ≥ 0):(dst – src << 1) OR 1 → dstElse:dst << 1 → dstO

Subtract Integer ConditionallySUBC13-227 Assembly Language InstructionsExample 1 SUBC @98C5h,R1Before Instruction After InstructionR1 00 0000 04F6

SUBFSubtract Floating-Point Value13-228 Syntax SUBF src, dstOperationdst – src →dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤

Subtract Floating-Point ValueSUBF13-229 Assembly Language InstructionsExample SUBF *AR0––(IR0),R5Before Instruction After InstructionR5 07 33C0 0000

SUBF3Subtract Floating-Point Value, 3-Operand13-230 Syntax SUBF3 src2, src1, dstOperationsrc1 – src2 → dstOperandssrc1 3-operand addressing modes (T)

Subtract Floating-Point Value, 3-OperandSUBF313-231 Assembly Language InstructionsExample 1 SUBF3 *AR0––(IR0),*AR1,R4Before Instruction After Instru

CPU Multiport Register File 3-6Table 3–2. Status Register Bits Bit Name Reset Value Name DescriptionC 0 Carry flag Carry condition flagV 0 Overflow fl

SUBF3||STFParallel SUBF3 and STF13-232 Syntax SUBF3src1, src2, dst1|| STF src3, dst2Operationsrc2 – src1 → dst1||src3 → dst2Operandssrc1register (Rn1

Parallel SUBF3 and STFSUBF3||STF13-233 Assembly Language InstructionsExample SUBF3 R1,*–AR4(IR1),R0|| STF R7,*+AR5(IR0)Before Instruction After Inst

SUBISubtract Integer13-234 Syntax SUBI src, dstOperationdst – src → dstOperandssrc general addressing modes (G):0 0 register (Rn, 0 ≤ n ≤ 27)0 1 dire

Subtract Integer, 3-OperandSUBI313-235 Assembly Language InstructionsSyntax SUBI3 src2, src1, dst Operationsrc1 – src2 → dstOperandssrc1 3-operand

SUBI3Subtract Integer, 3-Operand13-236 Example 1 SUBI3 R7,R2,R0Before Instruction After InstructionR0 00 0000 0000 R0 00 0000 0032R2 00 0000 0866 R2

Parallel SUBI3 and STISUBI3||STI13-237 Assembly Language InstructionsSyntax SUBI3src1, src2, dst1|| STI src3, dst2Operationsrc2 – src1 → dst1||src3

SUBI3||STIParallel SUBI3 and STI13-238 Example SUBI3 R7,*+AR2(IR0),R1|| STI R3,*++AR7Before Instruction After InstructionR1 00 0000 0000 R1 00 0000 00

Subtract Reverse Integer With BorrowSUBRB13-239 Assembly Language InstructionsSyntax SUBRB src, dstOperationsrc – dst – C → dstOperandssrc general

SUBRFSubtract Reverse Floating-Point Value13-240 Syntax SUBRF src, dstOperationsrc – dst →dstOperandssrc general addressing modes (G):0 0 register (R

Subtract Reverse IntegerSUBRI13-241 Assembly Language InstructionsSyntax SUBRI src, dstOperationsrc – dst → dstOperandssrc general addressing modes

Referencesvii Read This FirstDigital Signal Processing Applications with the TMS320 Family, Vol. III.Texas Instruments, 1990; Prentice-Hall, Inc., 1

CPU Multiport Register File3-7CPU RegistersTable 3–2. Status Register Bits (Continued)Bit Name DescriptionNameReset ValueCF 0 Cache freeze Enables or

SWISoftware Interrupt13-242 Syntax SWIOperation Performs an emulation interruptOperands NoneOpcode31 2423 16 8 7 01501100 01 01 0 0 000000000000000000

Trap ConditionallyTRAPcond13-243 Assembly Language InstructionsSyntax TRAPcond NOperation 0 → ST(GIE)If cond is true:Next PC → *++SP,Trap vector N →

TRAPcondTrap Conditionally13-244 Example TRAPZ 16Before Instruction After InstructionPC 0123 PC 0010SP 809870 SP 809871ST 0 ST 0LUF 0 LUF 0LV 0 LV 0U

Test Bit FieldsTSTB13-245 Assembly Language InstructionsSyntax TSTB src, dstOperationdst AND srcOperandssrc general addressing modes (G):0 0 regist

TSTBTest Bit Fields13-246 Example TSTB *–AR4(1),R5Before Instruction After InstructionR5 00 0000 0898 R5 00 0000 0898AR4 80 99C5 AR4 80 99C5LUF 0 LUF

Test Bit Fields, 3-OperandTSTB313-247 Assembly Language InstructionsSyntax TSTB3 src2, src1Operationsrc1 AND src2Operandssrc1 3-operand addressing

TSTB3Test Bit Fields, 3-Operand13-248 Example 1 TSTB3 *AR5––(IR0),*+AR0(1)Before Instruction After InstructionAR0 80 992C AR0 80 992CAR5 80 9885 AR5 8

Bitwise-Exclusive ORXOR13-249 Assembly Language InstructionsSyntax XOR src, dstOperationdst XOR src → dstOperandssrc general addressing modes (G):0

XOR3Bitwise-Exclusive OR, 3-Operand13-250 Syntax XOR3 src2, src1, dstOperationsrc1 XOR src2 → dstOperandssrc1 3-operand addressing modes (T):0 0 regi

Bitwise-Exclusive OR, 3-OperandXOR313-251 Assembly Language InstructionsExample 1 XOR3 *AR3++(IR0),R7,R4Before Instruction After InstructionR4 00 00

CPU Multiport Register File 3-8Table 3–2. Status Register Bits (Continued)Bit Name DescriptionNameReset ValuePRGW Dependenton PRGWpin levelProgram wid

XOR3||STIParallel XOR3 and STI13-252 Syntax XOR3 src2, src1, dst1|| STI src3, dst2Operationsrc1 XOR src2 → dst1||src3 → dst2Operandssrc1register (Rn1

Parallel XOR3 and STIXOR3||STI13-253 Assembly Language InstructionsStatus Bits These condition flags are modified only if the destination register i

A-1Appendix AInstruction OpcodesThe opcode fields for all TMS320C3x instructions are shown in Table A–1. Bitsin the table marked with a hyphen are def

Instruction OpcodesA-2 Table A–1. TMS320C3x Instruction Opcodes Instruction 31 30 29 28 27 26 25 24 23ABSF 0 0 0 0 0 0 0 0 0ABSI 0 0 0 0 00001ADDC 0

Instruction OpcodesA-3 Instruction OpcodesTable A–1. TMS320C3x Instruction Opcodes (Continued)Instruction 232425262728293031MPYI 0 0 0 0 1 0 1 0 1NE

Instruction OpcodesA-4 Table A–1. TMS320C3x Instruction Opcodes (Continued)Instruction 232425262728293031SUBRB 0 0 0 1 1 0 0 0 1SUBRF 0 0 0 1 10010SUB

Instruction OpcodesA-5 Instruction OpcodesTable A–1. TMS320C3x Instruction Opcodes (Continued)Instruction 232425262728293031RPTB 0 1 1 0 0 1 0 – –SW

Instruction OpcodesA-6 Table A–1. TMS320C3x Instruction Opcodes (Continued)Instruction 232425262728293031ABSI||STI 1 1 0 0 1 0 1 – –ADDF3||STF 1 1 0 0

B-1Appendix ATMS320C31 Boot Loader Source CodeThis appendix contains the source code for the ’C31 boot loader.Appendix B

TMS320C31 Boot Loader Source CodeB-2 ************************************************************************* C31BOOT – TMS320C31 BOOT LOADER PROG

CPU Multiport Register File3-9CPU Registers3.1.8 CPU/DMA Interrupt-Enable (IE) RegisterThe CPU/DMA interrupt-enable (IE) register of the ’C30, ’C31, a

TMS320C31 Boot Loader Source CodeB-3 TMS320C31 Boot Loader Source Code.global check.sect ”vectors”reset .word checkint0 .word 809FC1hint1 .word

TMS320C31 Boot Loader Source CodeB-4 trap11 .word 809FEBhtrap12 .word 809FEChtrap13 .word 809FEDhtrap14 .word 809FEEhtrap15 .word 809FEFhtrap16 .

TMS320C31 Boot Loader Source CodeB-5 TMS320C31 Boot Loader Source CodeNOP *AR1++(1) ; jump last half word from mem. wordLDI sub_h,AR3 ; half word si

TMS320C31 Boot Loader Source CodeB-6 LDI *+AR0(4Ch),R1LDI R0,R0 ; test load address flagBNN end_sload_s STI R1,*AR4++(1) ; store new word to dest. add

C-1Appendix ATMS320C32 Boot Loader Source CodeThis appendix includes a description of the ’C32 boot loader sequence ofevents and a listing of its sour

Boot-Loader Source Code DescriptionC-2 C.1 Boot-Loader Source Code DescriptionFigure C–1 shows the boot loader program flow chart. The boot loader pro

Boot-Loader Source Code DescriptionC-3 TMS320C32 Boot Loader Source CodeFigure C–1. Boot-Loader Flow ChartStartInitialize registers:AR7, SP, IR0Seri

Boot-Loader Source Code ListingC-4 C.2 Boot-Loader Source Code Listing********************************************************************************

Boot-Loader Source Code ListingC-5 TMS320C32 Boot Loader Source Code* that to function properly, the boot loader program always expects 32-bit *

Boot-Loader Source Code ListingC-6 * Test for INT3 and, if set exclusively, proceed with serial boot load. Else, * load AR3 with 1000h if INT0, 810000

CPU Multiport Register File 3-10Table 3–3. IE Bits and Functions AbbreviationResetValueDescriptionEINT0 (CPU) 0 CPU external interrupt 0 enableEINT1 (

Boot-Loader Source Code ListingC-7 TMS320C32 Boot Loader Source Codelabel4 SUBI 2,AR6 CMPI 0,AR6 ; set flags

Boot-Loader Source Code ListingC-8 CALLU AR0 ; 10 – STRB1 LDI R1,R4 AND 6Ch,R1

Boot-Loader Source Code ListingC-9 TMS320C32 Boot Loader Source Coderead_s0 TSTB 20h,IF ; look at RINT0 flag BZ read_

Boot-Loader Source Code ListingC-10 LDI 2,IOF ;*; assert data acknowledge ;*; (XF0 low to

D-1Appendix AGlossaryAA0–A23: External address pins for data/program memory or I/O devices.These pins are on the primary bus. address: The location o

GlossaryD-2 BK:Block-size register. A 32-bit register used by the ARAU in circular ad-dressing to specify the data block size.boot loader: An on-chip

GlossaryD-3 Glossarydata size: The number of bits (8, 16, or 32) used to represent a particularnumber.decode phase: The phase of the pipeline in whi

GlossaryD-4 IIACK:Interrupt acknowledge signal. An output signal indicating that an in-terrupt has been received and that the program counter is fetch

GlossaryD-5 GlossaryMmachine cycle: See CPU cycle.mantissa: A component of a floating-point number consisting of a fractionand a sign bit. The manti

GlossaryD-6 Ooverflow flag (OV) bit: A status bit that indicates whether or not an arithme-tic operation has exceeded the capacity of the correspondin

CPU Multiport Register File3-11CPU RegistersTable 3–3. IE Bits and Functions(Continued)Abbreviation DescriptionResetValueETINT0 (DMA) 0 DMA timer0 int

GlossaryD-7 GlossarySshort floating-point format: A 16-bit representation of a floating point num-ber with a 12-bit mantissa and a 4-bit exponent.sh

GlossaryD-8 Wwait state: A period of time that the CPU must wait for external program,data, or I/O memory to respond when it reads from or writes to t

IndexIndex-1Index16-bit-wide configured memory,TMS320C31 11-102-operand instruction 13-32-operand instruction word 8-253-operand addressing modes 2-17

IndexIndex-2 arithmetic logic unit (ALU), definition D-1assembler syntax expression, example 13-38assembly language, instruction set2-operand instruct

IndexIndex-3assembly language instructions (continued)normalize (NORM) 13-182–13-183parallel instructionsABSF and STF 13-42ABSI and STI 13-46ADDF3 and

IndexIndex-4 bitwise-logicalAND 13-623-operand 13-63with complement (ANDN) 13-67complement instruction (NOT) 13-184OR instruction 13-188blockdiagram,

IndexIndex-5carry bit, definition D-2carry flag 13-29central processing unit. See CPUcircular addressing 6-21–6-25algorithm 6-23buffer 6-21–6-25defini

IndexIndex-6 data-rate timing operationfixed 12-36burst mode 12-36continuous mode 12-36variable 12-39burst mode 12-35continuous mode 12-40data-page po

IndexIndex-7extended-precision(R7–R0) registers 3-3definition D-3floating-point format, definition D-3externalbuses (expansion, primary) 2-19interface

IndexIndex-8 global-control registerDMA 12-53–12-59serial port 12-15, 12-17–12-21timer 12-3, 12-4–12-6Hhandshake 11-20hardware interrupt, definition D

CPU Multiport Register File 3-12Figure 3–7. TMS320C30 CPU Interrupt Flag (IF) RegisterXINT1RINT1yy yy71115–1231–16xx10DINT9TINT18TINT05RINT04XINT03INT

IndexIndex-9interfaceenhanced memory, TMS320C32 2-19expansion bus 2-19primary bus 2-19interlockedinstructions 2-21operations 7-13–7-20busy-waiting loo

IndexIndex-10 logical shift instruction (LSH) 13-136LOPOWER 7-51–7-52timing 7-52low-powercontrol instructions 13-5idle instruction (IDLE2) 13-110LRU c

IndexIndex-11MSB, definition D-5MSTRB signal 9-3, 9-15multiple processors, sharing global memory 7-13multiplication, floating-point, examples 5-29–5-3

IndexIndex-12 peripherals 12-1–12-68DMA controller 12-48–12-68CPU/DMA interrupt enable regis-ter 12-59–12-62destination- and source-address regis-ters

IndexIndex-13program (continued)RPTB instruction 7-4–7-5RPTS instruction 7-5–7-6reset operation 7-21–7-25TMS320LC31 power management modeIDLE2 7-49–7-

IndexIndex-14 repeat end-address (RE) register 3-17, 7-2repeat mode, definition D-6repeat modes 7-2–7-8control algorithm 7-4control bits 7-3maximum nu

IndexIndex-15serial port (continued)loading 11-11memory mapped locations for 12-17operation configurations 12-29–12-31port control registerFSR/DR/CLKR

IndexIndex-16 timer-period register, definition D-7timingexternal interfaceexpansion bus I/O cycles 9-21–9-36primary bus cycles 9-15–9-20external memo

CPU Multiport Register File3-13CPU RegistersTable 3–4. IF Bits and FunctionsBitNameResetValueFunctionINT0 0 External interrupt 0 flagINT1 0 External i

CPU Multiport Register File 3-143.1.9.1 Interrupt-Trap Table Pointer (ITTP)Similar to the rest of the ‘C3x device family, the ’C32’s reset vector loca

CPU Multiport Register File3-15CPU RegistersFigure 3–11.Interrupt and Trap Vector LocationsEA (ITTP) + 3FhEA (ITTP) + 3EhEA (ITTP) + 3DhEA (ITTP) + 3C

CPU Multiport Register File 3-163.1.10 I/O Flag (IOF) RegisterThe I/O flag (IOF) register is shown in Figure 3–12 and controls the functionof the dedi

Referencesviii Parsons, Thomas., Voice and Speech Processing. New York, NY:McGraw Hill Company, Inc., 1987.Rabiner, Lawrence R., and Schafer, R.W., Di

CPU Multiport Register File3-17CPU Registers3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) RegistersThe repeat-counter (RC) register is a 32-bit

Other Registers 3-183.2 Other Registers3.2.1 Program-Counter (PC) RegisterThe program counter (PC) is a 32-bit register containing the address of then

Reserved Bits and Compatibility3-19CPU Registers3.3 Reserved Bits and CompatibilityTo retain compatibility with future members of the ’C3x family of m

4-1Memory and the Instruction CacheThe ’C3x provides a total memory space of 16M (million) 32-bit words that containprogram, data, and I/O space. Two

Memory 4-24.1 MemoryThe ’C3x accesses a total memory space of 16M (million) 32-bit words of pro-gram, data, and I/O space and allows tables, coefficie

Memory4-3Memory and the Instruction CacheMicrocomputer ModeIn microcomputer mode, the 4K on-chip ROM is mapped into locations0h–0FFFh. There are 192 l

Memory 4-4Figure 4–1. TMS320C30 Memory MapsReset, interrupt, trap vectors,and reserved locations (64)(external STRB active)0h03Fh040hExternalSTRB acti

Memory4-5Memory and the Instruction Cache4.1.1.2 TMS320C31 Memory MapThe memory map depends on whether the processor is running in micropro-cessor mod

Memory 4-6Figure 4–2. TMS320C31 Memory MapsReset, interrupt, trap vectors,and reserved locations (64)(external STRB active)0h03Fh040hExternalSTRB acti

Memory4-7Memory and the Instruction Cache4.1.1.3 TMS320C32 Memory MapThe memory map depends on whether the processor is running in micropro-cessor mod

Referencesix Read This FirstArray Signal ProcessingHaykin, S., Justice, J.H., Owsley, N.L., Yen, J.L., and Kak, A.C. Array SignalProcessing. Englewo

Memory 4-8Figure 4–3. TMS320C32 Memory MapsExternal memorySTRB1 active(7.168M words)External memorySTRB1 active(7.168M words)Boot 3External memorySTRB

Memory4-9Memory and the Instruction Cache4.1.2 Peripheral Bus Memory MapThe following sections describe the peripherial bus memory maps for the ’C30,’

Memory 4-10Figure 4–4. TMS320C30 Peripheral Bus Memory-Mapped RegistersSerial port 1 data transmit808064hPrimary-buscontrol808060hExpansion-buscontrol

Memory4-11Memory and the Instruction Cache4.1.2.2 TMS320C31 Peripheral Bus Memory MapThe ’C31 memory-mapped peripheral registers are located starting

Memory 4-124.1.2.3 TMS320C32 Peripheral Bus Memory MapThe ’C32’s memory-mapped peripheral and external-bus control registers arelocated starting at ad

Memory4-13Memory and the Instruction CacheFigure 4–6. TMS320C32 Peripheral Bus Memory-Mapped Registers8097FFh808068hSTRB1 buscontrol808064hSTRB0 busco

Reset/Interrupt/Trap Vector Map 4-144.2 Reset/Interrupt/Trap Vector MapThe addresses for the reset, interrupt, and trap vectors are 00h–3Fh, as showni

Reset/Interrupt/Trap Vector Map4-15Memory and the Instruction CacheFigure 4–7. Reset, Interrupt, and Trap Vector Locations for the TMS320C30 Microproc

Reset/Interrupt/Trap Vector Map 4-16Figure 4–8. Reset, Interrupt, and Trap Vector Locations for theTMS320C31 Microprocessor Mode00h RESET01h INT002h I

Reset/Interrupt/Trap Vector Map4-17Memory and the Instruction CacheFigure 4–9. Interrupt and Trap Branch Instructions for the TMS320C31Microcomputer M