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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Highest Performance Fixed-Point Digital

Signal Processor (DSP) TMS320C6202

– 4-ns Instruction Cycle Time

– 250-MHz Clock Rate

– Eight 32-Bit Instructions/Cycle

– 2000 MIPS

VelociTI Advanced Very Long Instruction

Word (VLIW) ’C6200 CPU Core

– Eight Highly Independent Functional

Units:

– Six ALUs (32-/40-Bit)

– Two 16-Bit Multipliers (32-Bit Result)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

Instruction Set Features

– Byte-Addressable (8-, 16-, 32-Bit Data)

– 32-Bit Address Range

– 8-Bit Overflow Protection

– Saturation

– Bit-Field Extract, Set, Clear

– Bit-Counting

– Normalization

3M-Bit On-Chip SRAM

– 2M-Bit Internal Program/Cache

– Two 128K-Byte Blocks Offer Improved

Concurrency

Block 0: 128K Bytes Memory-Mapped

Block 1: 128K Bytes Direct-Mapped

Cache/Memory-Mapped

– 1M-Bit Dual-Access Internal Data

(128K Bytes)

– Two 64K-Byte Blocks Offer Improved

Concurrency

32-Bit External Memory Interface (EMIF)

– Glueless Interface to Synchronous

Memories: SDRAM or SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

With an Auxiliary Channel

Flexible Phase-Locked-Loop (PLL) Clock

Generator

32-Bit Expansion Bus

– Glueless/Low-Glue Interface to Popular

PCI Bridge Chips

– Glueless/Low-Glue Interface to Popular

Synchronous or Asynchronous

Microprocessor Buses

– Master/Slave Functionality

– Glueless Interface to Synchronous FIFOs

and Asynchronous Peripherals

Three Multichannel Buffered Serial Ports

(McBSPs)

– Direct Interface to T1/E1, MVIP, SCSA

Framers

– ST-Bus-Switching Compatible

– Up to 256 Channels Each

– AC97-Compatible

– Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

Two 32-Bit General-Purpose Timers

IEEE-1149.1 (JTAG

†

)

Boundary-Scan-Compatible

352-Pin BGA Package (GJL Suffix)

384-Pin BGA Package (GLS Suffix)

0.18-µm/5-Level Metal Process

– CMOS Technology

3.3-V I/Os, 1.8-V Internal

ADVANCE INFORMATION

ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other

specifications are subject to change without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated.

Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

1 2 3 4 5 6 ... 73 74

ADVANCE INFORMATION 1

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IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic

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